Computational Memory Out-of-Phase Refresh for AI Inference

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Solution Overview

Problem

Current AI computation hardware faces bottlenecks due to data congestion and performance reduction caused by data movement between memory and CPU, exacerbated by issues like read disturb, retention loss, and endurance in existing memories, which are compounded by time-consuming data refresh operations that degrade inference accuracy and performance.

Innovation Solution

An electronic device with a computational memory comprising a first and second memory array, where both arrays store the same data and perform operations out of phase, allowing one to read while the other refreshes, thereby ensuring continuous data availability and accuracy without wasting time on refresh operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data refresh operation is performed to compensate retention loss, then data accuracy is improved, but time consumption increases and computing performance decreases

Engineering Contradiction:
Improvedata accuracyVSAvoidtime consumption
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The memory array is divided into multiple banks, allowing parallel operation of refresh and read tasks across different segments. This segmentation enables simultaneous execution of refresh operations on one bank while read operations occur on another bank, eliminating the time penalty of sequential refresh operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Refresh operations are performed in advance during idle periods or in parallel with computation tasks, ensuring data is refreshed before it is needed for computation. This preliminary action prevents data loss without interrupting the computational workflow.

Inventive Principle:
Principle #10Preliminary action

2Power

If data is stored in memory and transferred to CPU for computation, then computing capability is improved, but data congestion occurs and computing performance is reduced

Engineering Contradiction:
Improvecomputing capabilityVSAvoidcomputing performance
Core Design Contradiction:
PowerVSProductivity

Solution Approach 1:

The patent merges storage and computation functions into a single in-memory computing system. Compute-in-memory units are integrated directly within the memory array, allowing data to be processed in place without transfer to external CPU, thereby eliminating data congestion and improving overall computing performance.

Inventive Principle:
Principle #5Merging (Combining)

3Speed

If data is continuously read from memory, then computing speed is improved, but read disturb and retention loss occur

Engineering Contradiction:
Improvecomputing speedVSAvoiddata retention
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The system implements periodic refresh operations at predetermined intervals to counteract retention loss and read disturb effects. These periodic actions are scheduled to occur during computation tasks, ensuring data integrity is maintained without continuously interrupting the computational process.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20240363161A1Electronic device and method for operating the same
Publication Date: 2024.10.31 MACRONIX INTERNATIONAL CO LTD
  • US20240363161A1 patent drawing
  • US20240363161A1 patent drawing
  • US20240363161A1 patent drawing

AI summary

An electronic device is provided. The electronic device comprises a computational memory. The computational memory comprises a first memory array and a second memory array. The first memory array and the second memory array contain same data. The first memory array and the second memory array are configured to perform operations in an out of phase manner.