3D NAND Pseudo Block Operation Mode for Layer Variation Management
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Solution Overview
Problem
3D NAND memory devices face challenges in efficiently operating and managing storage elements due to variations in memory hole size, leading to issues with read disturb, endurance, and voltage stress across different layers, which affect performance and reliability.
Innovation Solution
Implementing a pseudo block operation mode where storage elements are grouped based on memory hole size, allowing for differentiated program and erase operations, read disturb management, and voltage application across pseudo blocks, enabling flexible and efficient operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If 3D NAND memory devices operate with uniform block structures across all layers, then device complexity is reduced, but performance and reliability deteriorate due to variations in memory hole size across layers
Solution Approach 1:
The patent divides the 3D NAND memory device into multiple pseudo-blocks, where each pseudo-block corresponds to a specific layer or group of layers with similar memory hole characteristics. This segmentation allows independent management of program-erase cycles and voltage application for each pseudo-block, addressing the reliability issues caused by inter-layer variations while maintaining manageable device complexity through structured organization.
Solution Approach 2:
The patent implements layer-dependent pseudo-block management where each pseudo-block has customized operation parameters (voltage levels, program-erase cycle counts, timing) tailored to its specific memory hole size characteristics. This local quality approach ensures that each layer operates under optimal conditions for its physical properties, improving overall device reliability without requiring complete uniformity across the entire structure.
2Reliability
If differentiated program and erase operations are applied to each layer, then data retention improves, but device complexity increases due to multiple operation modes
Solution Approach 1:
The patent introduces dynamic pseudo-block management where the memory device can adaptively select and switch between different operation modes based on the active pseudo-block being accessed. The controller dynamically adjusts program-erase cycle parameters, voltage levels, and timing sequences according to the specific layer characteristics, enabling differentiated operations without requiring permanent multiple fixed modes. This dynamic approach improves data retention while keeping device complexity manageable through software-controlled adaptability.
3Device complexity
If voltage is applied uniformly across all layers during program and erase operations, then device complexity is reduced, but read disturb and endurance variations worsen due to memory hole size differences
Solution Approach 1:
The patent implements localized voltage application where each pseudo-block receives customized voltage levels and waveforms tailored to its memory hole size characteristics. Smaller memory holes receive higher voltages for effective programming, while larger memory holes receive lower voltages to prevent excessive stress and read disturb. This local quality approach in voltage application reduces harmful effects while maintaining manageable device complexity through systematic voltage scheduling managed by the controller.
Data Source
AI summary
A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode.