Read-Only Memories TRIZ Cases

A memory device applies an additional program voltage to a first cell when an adjacent second cell remains in an erased status.

Dynamic page buffer sensing signal voltage levels optimize precharge and verify periods, decreasing program completion time while reducing peak current flow.

Determining a read window from accelerated program erase cycles compensates for degradation to improve data retention.

Stuck-at encoding mitigates inter-cell interference by forcing vulnerable least significant bits, reducing bit error rates.

A control circuit compares program data with read data to set inhibit bits and prevent redundant programming operations in nonvolatile memory cells.

A page buffer architecture isolates a cache latch from source line noise during program operations to protect stored data integrity.

Segments flash memory cells by current threshold voltage to apply tailored program pulses, eliminating programming time variation among slower elements.

Preprogram pulses narrow threshold voltage distribution, expanding the read window for accurate data distinction.

Dual e-fuse strings with a shared comparator enable multiple programming cycles by comparing voltages across the strings.

Overlaps voltage periods on adjacent word lines while applying distinct source line voltages to prevent current detection errors and logic misjudgment.

Flash memory applies distinct recovery voltages to unselected word lines, reducing threshold voltage distortion from hot carrier injection at edge word lines.

Iterative SSL-based erasing and verification improves data retention accuracy while preventing excessive device stress from high voltage.

An adjustable delay unit modifies clock signal timing to resolve CR delays from high load capacity, ensuring reliable data latching in stacked memory systems.

A control circuit writes a lower threshold level into memory cells to stabilize data storage in multilevel NAND flash arrays.

A twin-cell one-time-programmable memory structure uses error correction circuit flag bits and sense amplifier tilt to identify programmed states.

A memory device applies distinct voltages to selected and unselected bit lines during erasure operations.

Temperature-dependent body bias adjusts threshold voltage and sub-threshold slope in non-volatile memory, reducing read errors from widened distributions.

Location-based weighting distributes usage across memory blocks to prevent premature wear-out of low-endurance edge blocks.

A semiconductor memory device applies distinct voltages during separate sense periods to optimize verification speed.

Controller stores initial and shifted voltage values to adjust read thresholds, reducing error bits and latency without increasing memory size.

A trimming data read control circuit randomly selects memory regions to reduce access frequency.

A negative reference voltage generating circuit uses a differential amplifier driven by positive and negative power voltages to produce stable output.

An oxide semiconductor transistor eliminates refresh operations by suppressing leakage current, enabling non-volatile storage with high-speed writing.

A 3D NAND pseudo block operation mode groups storage elements by memory hole size to enable differentiated program and erase operations.

Adjusting erase voltages by block distance from pass gates to achieve uniform erase depth across memory cells.

Dynamic body bias adjustment compensates for manufacturing variations in integrated circuits, reducing power consumption while maintaining reliable performance.

A memory apparatus uses a control circuit to calculate program voltages based on erase upper tail voltage.