Memory System Control Circuit with Adjustable Delay for Signal Timing
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Solution Overview
Problem
In solid state drives (SSDs) with multiple stacked memory chips, increased load capacity of signal lines leads to delays in data read and output due to CR delays, causing issues with data latching and timing synchronization, especially in high-load states.
Innovation Solution
A memory system with a control circuit that includes a reading unit, a delay unit to adjust signal timing, and a latch unit using a programmable delay element to ensure reliable data output, even under high load conditions, by generating a second clock for data latch and adjusting the delay amount based on load capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked memory chips is increased to increase data capacity, then the data capacity is improved, but the load capacity of signal lines increases causing CR delay and data latching failure
Solution Approach 1:
The patent applies dynamics by making the clock signal timing adjustable rather than fixed. A delay amount adjustment unit dynamically adjusts the delay amount of the clock signal based on the number of stacked memory chips, allowing the system to adapt to varying load conditions while maintaining reliable data latching across different data capacity configurations
Solution Approach 2:
The patent changes the parameter of clock signal timing by introducing an adjustable delay amount. The delay amount adjustment unit modifies the delay characteristic of the clock signal path, changing the timing parameter to compensate for increased CR delay caused by higher signal line load capacity from stacked memory chips
2Quantity of substance
If the number of stacked memory chips is increased to increase data capacity, then the data capacity is improved, but the delay of read data increases due to increased load capacity
Solution Approach 1:
The patent changes the timing parameter of the clock signal by adjusting the delay amount. The delay amount adjustment unit modifies the delay characteristic to optimize the timing relationship between the read data signal and clock signal, compensating for the increased propagation delay caused by higher signal line load capacity
3Productivity
If a synchronously designed controller is used for low load state, then data can be latched and output efficiently, but data may not be latched and output in high load state due to CR delay
Solution Approach 1:
The patent transforms the static synchronous design into a dynamic system by introducing adjustable delay control. The delay amount adjustment unit enables the controller to adapt its timing characteristics based on load conditions, maintaining both high productivity in low-load states and reliable data latching in high-load states where CR delay becomes significant
Data Source
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AI summary
A memory system includes a nonvolatile memory, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that performs communication with a host according to an aspect of the preset invention, wherein the control circuit includes a reading unit that outputs a read enable signal to the nonvolatile memory to read data; a delay unit that delays a signal obtained by returning the read enable signal and outputs the signal as a clock, and a latch unit that latches and outputs the data read from the nonvolatile memory by using the clock output from the delay unit.