Memory Block Erase Depth Equalization via Distance-Dependent Voltage Control
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Solution Overview
Problem
In semiconductor memory devices, varying erase depths across different blocks due to distance from the pass gate of a voltage source lead to inconsistent programming and increased read errors, as closer blocks experience deeper erases while farther blocks have shallower erases, affecting programming efficiency and data integrity.
Innovation Solution
The erase operation is adjusted based on the distance of each block from the pass gates by modifying erase voltage widths, initial levels, and applying additional pulses, allowing for subsets of blocks to be erased uniformly, thereby compensating for the distance-related disparities in erase depth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a uniform erase voltage is applied to all blocks, then the erase operation is simple to implement, but blocks at different distances from the pass gate experience different erase depths leading to read errors
Solution Approach 1:
The patent applies different erase voltage characteristics (magnitude, duration, or number of pulses) to different blocks based on their distance from the pass gate. Blocks closer to the pass gate receive different erase parameters than blocks farther away, ensuring each block achieves the target erase depth despite position-dependent voltage attenuation. This local differentiation resolves the contradiction by maintaining data integrity through position-specific erasing while keeping the overall operation manageable.
Solution Approach 2:
The patent modifies erase operation parameters (voltage magnitude, pulse duration, or number of pulses) as a function of block distance from the pass gate. By dynamically adjusting these parameters based on position, the system compensates for voltage attenuation effects and achieves uniform erase depth across all blocks, thereby maintaining reliability without requiring overly complex control mechanisms.
2Manufacturing precision
If stronger erase voltages are applied to farther blocks to compensate for distance, then erase depth uniformity is improved, but energy consumption and device complexity increase
Solution Approach 1:
The patent adjusts erase voltage parameters (magnitude, duration, or pulse count) based on block distance, applying stronger or longer erases only to blocks that need them due to greater distance from the pass gate. This targeted parameter adjustment achieves erase depth uniformity while minimizing unnecessary energy expenditure on blocks that require less erasing power.
Solution Approach 2:
The patent applies erase voltages with varying intensity and duration tailored to each block's specific needs rather than using a uniform excessive voltage across all blocks. Blocks farther from the pass gate receive enhanced erase parameters, while closer blocks receive standard or reduced parameters, achieving uniformity without the energy cost of universally applying maximum erase strength.
3Manufacturing precision
If multiple different erase voltages are applied to different blocks, then erase depth consistency is improved, but control circuit complexity increases
Solution Approach 1:
The patent implements position-dependent erase characteristics where each block receives erase parameters tailored to its distance from the pass gate. The control circuit manages this differentiation through systematic addressing and parameter selection based on block position, achieving erase depth consistency while organizing complexity in a manageable, position-based framework rather than requiring complex adaptive control.
Solution Approach 2:
The patent pre-establishes erase parameter sets corresponding to different block positions or distance categories. The control circuit selects from these pre-defined parameter sets based on the target block's location, avoiding the need for complex real-time calculations or adaptive adjustments during the erase operation itself. This preliminary organization of erase strategies simplifies the control logic while maintaining precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures a more uniform erase depth across all blocks, reducing read errors and improving programming efficiency by tailoring erase voltages and pulses to each block's specific distance from the pass gate, leading to consistent data states and reduced program disturb.
Implementation Method 1
biasing the select gate transistor of each string of the selected block to generate holes in the channel by gate-induced drain leakage
Data Source
Figure 1A
Figure 1B
Figure 2
AI summary
A memory device and associated techniques provide a uniform erase depth for different blocks of memory cells which are at different distances from pass gates of a voltage source. In one approach, a voltage of a source side select gate transistor of a memory string is a decreasing function of the distance. In another approach, a magnitude or duration of an erase voltage at a source end of a memory string is an increasing function of the distance. Adjacent blocks can be arranged in subsets and treated as being at a common distance. In another approach, an additional erase pulse can be applied when the distance of the block exceeds a threshold. Other variables such as initial erase voltage and step size can also be adjusted as a function of distance.