Oxide Semiconductor Memory Cell Structure for Low Leakage
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Solution Overview
Problem
Existing semiconductor memory devices, such as DRAM and flash memory, face challenges with power consumption, data retention, and the limited number of write operations due to leakage currents and the need for high voltage.
Innovation Solution
A semiconductor device using a highly purified oxide semiconductor with extremely low leakage current, allowing for long-term data retention without the need for refresh operations or high voltage, and enabling high-speed data writing and reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a transistor is used in a DRAM memory element, then data can be stored in a capacitor, but leakage current causes charge loss requiring frequent refresh operations and increasing power consumption
Solution Approach 1:
The invention changes the fundamental parameter of the semiconductor material from conventional silicon-based materials to oxide semiconductor materials (such as In-Ga-Zn-O). This material parameter change results in extremely low off-state current (lower than 10^-21 A), which fundamentally resolves the leakage current problem in DRAM, eliminating the need for refresh operations and reducing power consumption to nearly zero during data retention.
Solution Approach 2:
The invention employs a capacitor structure with a simple parallel plate configuration using conductive layers and insulating layers, replacing complex transistor-based charge storage mechanisms. This simplified storage structure, combined with oxide semiconductor transistors having near-zero leakage, creates a memory element that maintains data without requiring active refresh, effectively making the storage system disposable of complex maintenance mechanisms.
2Duration of action of stationary object
If a flash memory uses a floating gate to store data, then data holding period becomes extremely long, but the gate insulating layer deteriorates due to tunneling current limiting the number of write operations
Solution Approach 1:
The invention changes the material parameter of the transistor from conventional silicon-based semiconductors to oxide semiconductors (In-Ga-Zn-O). This material parameter change eliminates the need for high-voltage tunneling current by using normal conduction mechanisms, thereby preventing gate insulating layer deterioration while maintaining extremely long data retention periods.
Solution Approach 2:
The invention substitutes the tunneling current mechanism (quantum mechanical effect) with normal conduction control in oxide semiconductor transistors. Instead of using high-voltage electron injection through tunneling to store data in a floating gate, the system uses controlled charge storage in a simple capacitor, accessed by the oxide semiconductor transistor's on/off state, eliminating mechanical stress and degradation on insulating layers.
3Reliability
If a flash memory requires high voltage for charge injection and removal, then data can be stored non-volatilely, but writing and erasing operations become slower and require additional high voltage generation circuits
Solution Approach 1:
The invention changes the electrical parameter requirements by using oxide semiconductor transistors that operate at standard voltages (0-5V) instead of high voltages (10-20V). The oxide semiconductor's extremely low off-state current and high on-state mobility enable reliable data storage and fast switching at normal operating voltages, eliminating the need for high-voltage generation circuits and enabling faster write/erase operations.
Solution Approach 2:
The invention substitutes the high-voltage tunneling mechanism with low-voltage field effect control in oxide semiconductor transistors. Data is written by controlling the oxide semiconductor transistor's channel conductivity through standard voltage gates, which then controls charge flow to the capacitor. This eliminates the need for high-voltage stress and complex voltage generation, enabling faster and simpler write operations.
4Duration of action of stationary object
If an SRAM uses a flip-flop circuit to hold data, then refresh operations are not needed, but the cost per storage capacity increases
Solution Approach 1:
The invention extracts and removes the complex flip-flop circuit structure from the memory element, replacing it with a simple capacitor for charge storage controlled by an oxide semiconductor transistor. The oxide semiconductor's near-zero leakage current inherently provides the refresh-free operation normally requiring complex feedback circuits, thereby simplifying the device structure while maintaining SRAM-like advantages.
Solution Approach 2:
The invention uses a simple capacitor structure with conductive and insulating layers instead of complex flip-flop circuits. Combined with the oxide semiconductor transistor's extremely low leakage, this simplified storage element achieves refresh-free operation without requiring the expensive and complex feedback circuitry of SRAM, reducing device complexity and manufacturing cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device achieves reduced power consumption, extended data retention, and increased reliability by eliminating the need for refresh operations and high voltage, while allowing for high-speed data operations.
Implementation Method 1
a semiconductor layer which includes an oxide semiconductor and has a thickness of 3 nm or more and 30 nm or less
Data Source
AI summary
An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.