Nonvolatile Memory Erase Verification by String Selection Line

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Current nonvolatile memory devices face challenges in efficiently verifying and performing erasing operations across a memory block, particularly in ensuring data retention and error handling in 3D array structures.

Innovation Solution

A method and device configuration that involves verifying erasing operations across multiple string selection lines, adjusting erase voltage, and using a control logic with counters and latches to manage and report errors, ensuring comprehensive erasure and data integrity in a 3D memory cell array.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If erasing operation is performed to all memory cells associated with multiple SSLs simultaneously, then erasing speed is improved, but verification accuracy deteriorates due to inability to track and verify each SSL individually

Engineering Contradiction:

Improveerasing speedVSAvoidverification accuracy

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent segments the erasing and verification process by SSL. The control logic iterates through each SSL individually, performing erasing and verification operations for one SSL at a time. This segmentation allows simultaneous improvement of both erasing speed (by systematically processing multiple SSLs) and verification accuracy (by tracking each SSL's verification status individually through the SSL counter and verification logic)

Inventive Principle:

Principle #1Segmentation

2Reliability

If verification is performed for each SSL individually, then verification accuracy is improved, but total operation time increases

Engineering Contradiction:

Improveverification accuracyVSAvoidtotal operation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent maintains continuous useful action by implementing an iterative process that immediately follows erasing with verification for each SSL without interruption. The control logic continuously cycles through SSLs, performing erasing then verification in sequence, ensuring no time is wasted and both operations are completed efficiently while maintaining high verification accuracy

Inventive Principle:

Principle #20Continuity of useful action

3Reliability

If erase voltage is increased to ensure complete erasure, then erasing effectiveness is improved, but device stress increases leading to potential damage

Engineering Contradiction:

Improveerasing effectivenessVSAvoiddevice stress

Core Design Contradiction:

ReliabilityVSStress or pressure

Solution Approach 1:

The patent implements feedback through verification operations after each erasing cycle. The control logic applies erase voltage to a memory block, then verifies the erasure result by checking if memory cells associated with the current SSL are properly erased. Based on this feedback, the system determines whether to continue applying erase voltage or stop, thereby ensuring complete erasure effectiveness while avoiding excessive device stress from unnecessary high-voltage application

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS9947416B2Nonvolatile memory device, operating method thereof and memory system including the same

Publication Date: 2018.04.17 SAMSUNG ELECTRONICS CO LTD

AI summary

A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.