NAND Flash Memory Erasing via Selective Bit Line Voltage Control
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Solution Overview
Problem
Traditional NAND flash memory erasing schemes are inefficient due to the need to write residual page data to another memory block before erasing, leading to increased time in garbage collection and wear leveling.
Innovation Solution
The memory device and method divide bit lines into selected and unselected groups, applying a first voltage to erase data on selected bit lines while setting unselected memory strings to float with a second voltage, preventing data erasure and optimizing erasing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If block-based erasing scheme is used to erase all pages in a memory block, then complete data erasure is achieved, but time for garbage collection and wear leveling increases significantly
Solution Approach 1:
The patent segments the memory block into multiple memory strings and further divides them into selected and unselected groups. By applying different voltages to different bit lines connected to these groups, the erasing operation is segmented to affect only selected memory strings, thereby reducing the overall erasure time while maintaining data integrity.
Solution Approach 2:
The patent applies local quality by using different voltage conditions on different bit lines within the same memory block. Selected bit lines receive voltages that enable erasure, while unselected bit lines maintain conditions that prevent erasure. This localized differentiation allows partial erasure of only necessary memory strings, reducing garbage collection time.
2Reliability
If block-based erasing scheme is used to erase all pages in a memory block, then complete data erasure is achieved, but time for wear leveling increases significantly
Solution Approach 1:
The patent segments the memory block into multiple memory strings and further divides them into selected and unselected groups. By applying different voltages to different bit lines connected to these groups, the erasing operation is segmented to affect only selected memory strings, thereby reducing the overall erasure time while maintaining data integrity.
Solution Approach 2:
The patent applies local quality by using different voltage conditions on different bit lines within the same memory block. Selected bit lines receive voltages that enable erasure, while unselected bit lines maintain conditions that prevent erasure. This localized differentiation allows partial erasure of only necessary memory strings, reducing wear leveling time.
3Reliability
If all pages in a memory block are erased, then data erasure is complete, but residual page data must be written to another memory block first
Solution Approach 1:
The patent segments the memory block into multiple memory strings and further divides them into selected and unselected groups. By applying different voltages to different bit lines connected to these groups, the erasing operation is segmented to affect only selected memory strings, thereby reducing the overall erasure time while maintaining data integrity.
Solution Approach 2:
The patent extracts the unnecessary step of writing residual data to another memory block by enabling selective erasure. By identifying and erasing only the specific memory strings that need erasure while leaving others intact, the system eliminates the need for data migration, simplifying the overall process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces time in garbage collection and wear leveling, enhancing the efficiency of the erasing process by selectively controlling voltages to prevent unnecessary data erasure across memory strings.
Implementation Method 1
a first voltage is applied to the first bit line to erase data stored in the first memory string
Implementation Method 2
a second voltage is applied to the second bit line to set the second memory string to be floating
Data Source
AI summary
A memory device comprises a first memory string and a second memory string. The first memory string is coupled to a first bit line and a plurality of word lines, and the second memory string is coupled to a second bit line and the word lines. When an erasing voltage is applied to the word lines, a first voltage is applied to the first bit line to erase data stored in the first memory string, and a second voltage is applied to the second bit line to set the second memory string to be floating.