Nonvolatile Memory Page Buffer Noise Immunity
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Solution Overview
Problem
Existing page buffers in non-volatile memory devices are susceptible to noise and voltage surges on the source line, leading to potential program failures during program operations, as the cache latch is directly connected to the source line, causing bits to be flipped and resulting in 'permanent inhibit' conditions where cells are incorrectly recognized as programmed.
Innovation Solution
The page buffer architecture isolates the cache latch from the source line during program and program-verify operations, using a temporary latch for data transfer between the cache and main latches, ensuring that noise and voltage surges do not affect the bit stored in the cache latch, thus preventing incorrect programming and maintaining the 'cache program' functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the cache latch is directly connected to the source line for efficient data transfer, then programming speed is improved, but noise and voltage surges on the source line can flip bits in the cache latch causing program failures
Solution Approach 1:
A temporary latch is introduced as an intermediary component between the cache latch and the source line. The temporary latch receives data from the cache latch and transfers it to the main latch, while being isolated from direct connection to the source line during program operations. This intermediary structure allows efficient data transfer to proceed while protecting the critical latch data from noise and voltage surges on the source line.
2Reliability
If the cache latch is isolated from the source line during program operations, then noise immunity is improved, but data transfer between cache and main latches becomes more complex
Solution Approach 1:
The latch structure is segmented into three distinct components: cache latch, temporary latch, and main latch. Each latch serves a specific function in the data transfer chain. The temporary latch acts as a buffer that segments the direct connection between cache and main latches, allowing isolation from the source line while maintaining data flow. This segmentation reduces complexity by creating modular, functionally distinct units rather than a monolithic structure.
3Reliability
If a temporary latch is added for data transfer, then bit storage reliability is improved, but silicon area occupation increases
Solution Approach 1:
The temporary latch is designed to perform multiple functions: it serves as a data buffer during program operations, provides isolation from source line noise, and enables sequential data transfer from cache to main latch. By making the temporary latch multi-functional, the design achieves improved reliability without requiring additional dedicated components, thereby minimizing the increase in silicon area occupation.
Data Source
AI summary
A nonvolatile memory device implements a program routine followed by a program-verify routine when recording or modifying stored data. The nonvolatile memory device may include an array of memory cells for storing data, a sense node, and a gating circuit for selectively connecting a bitline of the array of memory cells to the sense node. The nonvolatile memory device may also include a page buffer coupled to the sense node. The page buffer may include a main latch for storing data to be written in the nonvolatile memory device, a cache latch for storing data supplied on an input line of the nonvolatile memory device to be transferred in the main latch through a source liner and a temporary static latch connected to the main latch through the source line and to the cache latch through an auxiliary switch and for transferring data between the main latch and the cache latch. The cache latch may be isolated from the source line during execution of the program routine and of the program-verify routine.