Memory Apparatus Using Zero Pulse Smart Verify
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Solution Overview
Problem
Non-volatile memory devices face challenges in determining optimal program voltages as they undergo repeated programming and erasing cycles, leading to inefficiencies in programming speed and accuracy.
Innovation Solution
A control circuit or controller is used to determine the erase upper tail voltage of memory cells after an erase operation, which corresponds to their cycling condition, and calculates a program voltage to apply to selected word lines for programming, ensuring threshold voltages remain within a common range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed program voltage is used for programming memory cells, then the programming process is simple, but the programming accuracy deteriorates as memory cells undergo repeated programming and erasing cycles
Solution Approach 1:
The patent implements dynamic adjustment of program voltage based on the cycling condition of memory cells. The control circuit determines the cycling condition by analyzing the distribution of threshold voltages after erase operations and adjusts the program voltage accordingly. This dynamic approach allows the system to maintain optimal programming accuracy across different cycling stages without requiring complex pre-characterization procedures.
Solution Approach 2:
The patent changes the program voltage parameter based on the cycling condition of memory cells. By monitoring threshold voltage distribution and determining the cycling condition, the system adjusts the program voltage to compensate for wear effects. This parameter adjustment enables the system to maintain programming accuracy as memory cells undergo repeated programming and erasing cycles.
2Manufacturing precision
If the program voltage is adjusted to maintain accuracy across cycling conditions, then programming accuracy is improved, but the programming speed deteriorates due to additional voltage determination steps
Solution Approach 1:
The patent performs preliminary determination of the cycling condition by analyzing threshold voltage distribution after erase operations. This preliminary action provides the control circuit with information about the memory cells' state before programming begins, enabling optimal program voltage selection from the outset. By determining the cycling condition in advance, the system avoids iterative voltage adjustments during programming, thus maintaining high programming speed while ensuring accuracy.
Solution Approach 2:
The patent implements a feedback mechanism where the control circuit monitors threshold voltage distribution after erase operations and uses this information to determine the cycling condition. This feedback loop enables the system to adaptively select the appropriate program voltage based on the actual state of memory cells, ensuring both accuracy and efficiency without requiring multiple trial programming passes.
3Manufacturing precision
If multiple program voltages are used to account for different cycling conditions, then programming accuracy across all conditions is improved, but the device complexity increases due to additional control circuitry and voltage selection logic
Solution Approach 1:
The patent uses a control circuit that determines cycling condition by analyzing threshold voltage distribution characteristics and selects appropriate program voltage from a set of predefined voltages. This approach allows the system to maintain multiple voltage options for different cycling conditions while keeping the control logic relatively simple, as the voltage selection is based on straightforward analysis of threshold voltage distribution after erase operations.
Data Source
AI summary
A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells. Each of the memory cells is connected to one of a plurality of word lines and are also arranged in strings and configured to retain a threshold voltage within a common range of threshold voltages. A control circuit coupled to the plurality of word lines and the strings is configured to determine an erase upper tail voltage of a distribution of the threshold voltage of the memory cells following an erase operation. The erase upper tail voltage corresponds to a cycling condition of the memory cells. The control circuit is also configured to calculate a program voltage to apply to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells during a program operation based on the erase upper tail voltage.