NOR Flash Memory Word Line Control for Fast Read Speed
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Solution Overview
Problem
The switching speed between word lines in NOR flash memory devices is slowed due to the electrical conduction speed of polycrystalline silicon, causing bottlenecks in memory reading speed, especially when using fast read commands, as simultaneous voltage application to adjacent word lines results in incorrect current detection and logic misjudgment.
Innovation Solution
A control method for a memory device that synchronizes the voltage application to word lines across rows, allowing the period of voltage for a target memory cell to overlap with the adjacent row, while using distinct voltages for source lines to prevent incorrect current detection, thereby ensuring accurate reading of target memory cells without affecting adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the word line controller simultaneously provides voltage to the word line corresponding to the target memory cell and the word line corresponding to the next row, then the word line switching time is reduced, but the current detection accuracy deteriorates causing logic misjudgment
Solution Approach 1:
The patent segments the source line control into two independent controls: one for the current row's source line and another for the next row's source line. This allows independent voltage application to different source lines, enabling the word line controller to simultaneously activate multiple word lines while the source line controller selectively enables current flow only through the target memory cell's source line, thus maintaining detection accuracy while reducing switching time
Solution Approach 2:
The source line controller acts as an intermediary between the word line controller and the memory cells. It receives control signals and selectively applies voltages to different source lines, thereby mediating the current flow to ensure that even when multiple word lines are activated simultaneously, current flows only through the intended target memory cell, preventing detection errors
2Measurement precision
If the word line controller switches between different word lines sequentially, then the current detection accuracy is maintained, but the memory reading speed deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-enabling the next row's source line controller in advance during the read operation. This allows the word line controller to switch to the next word line more quickly without waiting for source line reconfiguration, as the next source line is already prepared and enabled, thus improving reading speed while maintaining detection accuracy through controlled current flow
Solution Approach 2:
The patent introduces dynamic control where the source line voltage is adjusted in real-time based on the read operation progress. The source line controller dynamically switches voltages between different source lines during the read process, allowing flexible and rapid transitions that improve reading speed while ensuring accurate current detection through proper timing and voltage sequencing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces the time required for word line switching during read commands and improves overall reading efficiency by ensuring only the target memory cell is read, avoiding misjudgment and maintaining accurate logic determination.
Implementation Method 1
the electrical conduction speed of the polycrystalline silicon is not as fast as bit lines made of metal
Data Source
AI summary
A control method of a memory device is provided. When a target memory cell whose source is connected to a first source line needs to be read, a word line controller provides a first voltage to a word line corresponding to the target memory cell and also provides the first voltage to a word line corresponding to the next row of the target memory cell, so that the period when the word line corresponding to the target memory cell remains at the first voltage overlaps the period when the word line corresponding to the next row of the target memory cell remains at the first voltage. When the target memory cell needs to be read, a source line controller provides a second voltage to the first source line, and provides a third voltage to the second source line; the third voltage is not equal to the second voltage.