NAND Flash Memory Cell Write Sequence Control for Threshold Voltage Stability
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Solution Overview
Problem
In NAND flash memory, writing data into adjacent cells causes fluctuations in the threshold voltage of already written cells due to coupling between floating gates, making it difficult to maintain stable data storage in multilevel cells.
Innovation Solution
A semiconductor memory device with a control circuit that writes a threshold level lower than the original level into a first memory cell and adjusts the threshold level of adjacent cells accordingly, preventing fluctuations by writing data in a specific sequence and using dummy cells to prevent erroneous programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is written into adjacent cells in multilevel memory, then storage capacity is improved, but threshold voltage stability of already written cells deteriorates due to floating gate coupling
Solution Approach 1:
The control circuit determines in advance whether adjacent cells will be written consecutively before writing data into the current cell. Based on this preliminary determination, it selects the appropriate write mode (normal or suppressed) to prevent threshold voltage fluctuations caused by subsequent adjacent cell writes.
Solution Approach 2:
The patent changes the write voltage parameter dynamically based on the write sequence. When adjacent cells are not written consecutively, the control circuit suppresses the write operation to maintain the original threshold voltage level. When adjacent cells are written consecutively, normal write operations are performed to improve storage capacity.
2Productivity
If write speed is increased in multilevel memory, then productivity is improved, but threshold voltage control precision deteriorates due to coupling effects
Solution Approach 1:
The control circuit dynamically adjusts the write operation based on real-time conditions. It monitors whether adjacent cells will be written consecutively and automatically switches between normal write mode (for speed) and suppressed write mode (for precision), making the write process adaptive rather than static.
Solution Approach 2:
The control circuit uses feedback from the write sequence determination to adjust subsequent write operations. By determining in advance whether adjacent cells will be written consecutively, the system can proactively adjust write parameters to maintain precision without sacrificing overall productivity.
3Reliability
If all cells in NAND cell are written to complete data writing, then storage completeness is improved, but time to write data into a specific cell increases
Solution Approach 1:
The patent segments the write operation into different modes based on the write sequence. Instead of uniformly writing to all cells, the control circuit divides the write process into suppressed writes (for non-consecutive adjacent cells) and normal writes (for consecutive adjacent cells), optimizing the overall write time while maintaining data completeness.
Data Source
AI summary
In a memory cell array, a plurality of memory cells are arranged in a matrix. Each of the plurality of memory cells stores one of a plurality of threshold levels. When writing one of the plurality of threshold levels into a first memory cell of the memory cell array, a control circuit writes a threshold level a little lower than the original threshold level. When not writing a second memory cell adjacent to the first memory cell consecutively, the control circuit writes the original threshold level into the first memory cell.