Semiconductor Memory Sense Amplifier Voltage Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving faster operation and efficient data verification due to limitations in voltage control and capacitance requirements for sense amplifiers, leading to prolonged verification times.
Innovation Solution
The semiconductor memory device incorporates a sense amplifier circuit with a control unit that applies distinct voltages during different sense periods, utilizing a series connection of transistors and a voltage generation circuit to optimize voltage levels and reduce verification time by indexing failed and passed cell transistors simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a sense amplifier circuit uses multiple voltage levels for verification, then measurement precision is improved, but loss of time increases due to prolonged verification times
Solution Approach 1:
The patent applies periodic action by dividing the verification process into two distinct sense periods: a first sense period using a first voltage level, and a second sense period using a second voltage level. This periodic switching between different voltage levels allows the circuit to efficiently classify cell transistors into passed and failed categories without requiring continuous monitoring at multiple voltage levels simultaneously, thereby reducing total verification time while maintaining measurement precision.
Solution Approach 2:
The patent employs dynamics by making the voltage level applied to the sense amplifier circuit dynamic rather than static. The control unit dynamically switches between a first voltage level during the first sense period and a second voltage level during the second sense period. This dynamic voltage adjustment allows the same hardware circuit to perform multiple verification functions at different stages, improving time efficiency while maintaining the precision needed to distinguish between passed and failed cell transistors.
2Speed
If the sense amplifier circuit requires high capacitance for fast operation, then speed is improved, but use of energy increases
Solution Approach 1:
By using periodic action with two distinct sense periods at different voltage levels, the patent enables the sense amplifier circuit to complete verification tasks more efficiently. The first sense period at the first voltage level performs initial verification, and the second sense period at the second voltage level completes the classification. This periodic approach reduces the total time required for verification, thereby improving operation speed without requiring the sense amplifier to maintain high capacitance continuously, thus reducing overall energy consumption.
Data Source
AI summary
A semiconductor memory device includes a memory cell transistor, a bit line, a sense amplifier circuit, a voltage generation circuit, and a control unit. The bit line is electrically connected to a terminal of the memory cell transistor. The sense amplifier circuit includes a first transistor having a gate electrically connected to the bit line and a second transistor connected in series to a first terminal of the first transistor. The control unit controls the voltage generation circuit to apply a first voltage to the second terminal of the first transistor during a first sense period and a second voltage to the second terminal of the first transistor during a second sense period. The first voltage is equal to or higher than 0 V and the second voltage is higher than 0 V, and the first and second voltages have voltage levels different from each other.