3D NAND Read Disturb Suppression via Select Gate Control
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Solution Overview
Problem
In 3D stacked non-volatile memory devices, the read operation can cause read disturb in unselected memory cells due to channel boosting, leading to errors and performance issues, particularly when cells have high threshold voltages.
Innovation Solution
The solution involves temporarily making select gates conductive during the read operation to control and reduce channel boosting, preventing both normal and weak-erase type read disturbs by maintaining a lower channel potential in unselected strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If channel boosting is applied during read operation to maintain proper memory cell operation, then read operation reliability is improved, but unselected memory cells experience read disturb leading to data errors
Solution Approach 1:
The patent applies different voltage levels to different groups of memory cells during the read operation. Specifically, unselected memory cells are maintained at a first voltage level while selected memory cells are switched to a second voltage level for sensing. This local differentiation prevents read disturb in unselected cells while enabling proper read operation in selected cells.
Solution Approach 2:
The memory cell array is divided into multiple groups, with unselected groups maintained at a stable voltage level and selected groups switched to a different voltage level for sensing. This segmentation allows the read operation to be performed on specific groups without affecting other groups, thereby preventing read disturb.
2Measurement precision
If high threshold voltage memory cells are read using conventional methods, then data in selected cells can be sensed, but channel boosting causes weak-erase type read disturb in unselected cells
Solution Approach 1:
The patent implements local quality control by maintaining unselected memory cells at a stable first voltage level while only switching selected memory cells to a second voltage level for sensing. This prevents the channel boosting effect from affecting unselected cells, thereby preserving data retention reliability while still enabling accurate threshold voltage sensing in selected cells.
Solution Approach 2:
The patent dynamically switches the voltage level of selected memory cells from a first level to a second level only when needed for sensing, while unselected memory cells remain at the stable first voltage level throughout the operation. This dynamic control enables precise measurement of selected cells without causing read disturb to unselected cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses read disturb, ensuring accurate data retention and improved memory device performance by optimizing channel boosting levels.
Implementation Method 1
During a read operation, unselected memory cells in the block can experience a read disturb due to a capacitive coupling from a control gate of the memory cell to a channel of the memory cell
Implementation Method 2
applying a control gate read voltage to the selected memory cells, and sensing whether a threshold voltage of the at least one of the selected memory cells is above the control gate read voltage by sensing whether the at least one selected string of memory cells is in a conductive state
Data Source
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Figure 1B
Figure 1C
AI summary
A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made non- conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can oocur by making the drain-side and/or source-side select gates conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosing drives the channel at Vbl, then provides boosting by capacitive coupling.