Solid-State Devices TRIZ Cases

A flat display device extends pixel electrodes to cover data lines and gate lines while adding dummy pixels in the peripheral region.

An in-cell OLED touch display panel structure integrates a metal sensing electrode layer between substrates to enable direct touch input detection.

Metal catalyst and solid phase crystallization grow large uniform crystals in the semiconductor layer, improving leakage and driving currents.

Shared electrode and etching stop layers increase capacitance while reducing parasitic capacitance in the display panel.

Curved light blocking structures formed by isotropic etching reduce pixel crosstalk and dark current, improving quantum efficiency.

Vertical stacking of row control cells beneath phase change memory cells reduces planar footprint and programming errors by managing current distribution.

Vertical selection transistors with semiconductor pillars reduce punch-through leakage and cell size to 4F^2.

Ion irradiation increases density at the chalcogenide layer interface, preventing void formation and maintaining memory cell reliability.

A transparent resin composition suppresses dark spots by shielding moisture while maintaining flexibility.

Segmented bottom electrode contacts surrounded by insulating layers isolate phase-change material patterns.

A graded recombination layer with a work function gradient facilitates efficient charge carrier recombination between photovoltaic junctions.

A triple-layer metal wire structure uses an upper protective layer to shield intermediate materials during photolithography patterning.

Thermal compression bonding of a pre-formed concave glass member seals the LED chip at lower temperatures, preventing die adhesion and resin degradation.

Sandwich wafer between suction pad and chuck table to relieve internal stress before laser processing.

Spirobifluorenyl amines in the hole-transporting layer enhance OLED efficiency and lifetime.

A resistive change element array groups multiple memory cells under a single selection device to increase storage density.

Adjustable back gate bias voltages set transistor capacitance in millimeter wave power amplifiers.

Radially peaked electric fields multiply single photons in silicon, balancing detection speed and noise without extra doped regions.

Tapered recess side surfaces reflect incident light onto pixel regions, reducing substrate absorption and improving light sensitivity.

Shared select gates merge control functions to increase memory cell density while reducing leakage current.

A vertical pillar semiconductor device uses a stress providing layer to induce lattice deformation in the channel.

Annular and peripheral openings in a silicon nitride bilayer dielectric barrier layer vent hydrogen to prevent PBTI threshold voltage shifts.

Insulating fences on contact hole walls prevent electric shorts between bit line contacts while maintaining insulation integrity.

Opposite polarity voltage pulses cancel threshold drift in chalcogenide memory, restoring cell selectability and enabling reliable programming.

A display panel uses a scattering layer between the light-emitting substrate and photoresist to redirect emitted light.

Segmented ground layers resolve signal loss and antenna density contradictions by providing dedicated references across multiple substrate levels.

A light-emitting element wafer uses isolation trenches extending through the luminescent layer to define independent processing zones for each semiconductor element.

Separating host and dopant into distinct layers prevents non-uniform doping, resolving color reliability deterioration and lifespan reduction.

PBLZT materials enable optical polarization switching, reducing leakage current and heat dissipation in miniaturized memory devices.

A segmented holding structure grips micro LEDs at the top surface edge to enable precise pick-up and placement on receiving substrates.

A trench memory structure filled with a single monolithic conducting material layer.

A semiconductor device uses a top-side current distribution structure to deliver lateral electrical flow across the active zone.

In situ steam generation forms the top blocking oxide layer to eliminate batch-to-batch thickness variation caused by phosphoric acid etching.

A multilayer capacitor uses a FASS-curve trench structure to form electrodes on complex three-dimensional surfaces.

Segmenting the memory array into blocks with dedicated data lines reduces parasitic coupling capacitance while maintaining high cell density.

A touch input device detects pressure using capacitance changes between electrodes.

A vertical LED lighting device uses series-connected electrodes to achieve high power output with reduced current requirements.

A semiconductor storage device uses a stacked body and columnar body configuration to form memory cells at intersections.

Roughened light coupling layers mitigate lattice mismatch stresses on silicon substrates, preventing cracking while improving light extraction efficiency.

A metallic assist structure provides rotating spin transfer torque to the free layer of a magnetic memory device.

A semiconductor manufacturing method uses a variable-thickness resist mask to define heavily and lightly doped regions simultaneously.

Annealing amorphous indium gallium tin oxide films at 500 to 800 C produces c-axis oriented crystalline structures.

A 3D NAND read process controls channel boosting through select gate voltage management to suppress data errors in unselected memory strings.

A charge block layer with a work function adjustment layer and diffusion suppression layer stabilizes organic photoelectric conversion devices.

A pressure sensor uses individual electrodes with varying thicknesses to create distinct gaps from a common pressure-sensitive layer.

Dislocated sub-pixel arrangements widen metal mask openings, strengthening mechanical stability against deformation while maintaining high resolution.

Segmenting the staircase into x and y direction steps reduces lateral dimensions while maintaining storage capacity per unit area.

A semiconductor memory device integrates volatile memories as latch circuits within a laminated structure to enhance data handling efficiency.