Memory Array Data Line Architecture for Capacitance Reduction
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Solution Overview
Problem
The increasing density of memory cells in memory devices poses challenges in designing circuitry and interconnections, particularly in efficiently accessing and managing data within a limited device size.
Innovation Solution
The implementation of a memory device architecture that includes a memory array with select and bias circuits, which selectively couple data lines to sense amplifiers and different voltages during various operations, optimizing data access and storage while reducing undesired coupling capacitance between adjacent lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased for a given device size, then storage capacity is improved, but designing circuitry and interconnections becomes more challenging and complex
Solution Approach 1:
The memory array is divided into multiple blocks, with each block having its own dedicated data line. This segmentation allows independent access to different memory blocks, reducing the complexity of interconnections needed to access the entire memory array while maintaining high density.
Solution Approach 2:
The patent introduces a block-select dimension by organizing memory into multiple blocks that can be independently selected. This adds a hierarchical level to the addressing scheme, allowing efficient access to high-density memory arrays without requiring excessively complex direct routing to every cell.
2Productivity
If more data lines are added to access higher density memory cells, then data access capability is improved, but coupling capacitance between lines increases
Solution Approach 1:
By segmenting the memory array into blocks with dedicated data lines, the total capacitance on each individual data line is reduced compared to a fully interconnected architecture. This allows more data lines to be used for accessing high-density cells without each line suffering from excessive coupling capacitance to all other lines.
Solution Approach 2:
Each data line is optimized for its specific memory block, with coupling capacitance primarily limited to adjacent lines within the same block rather than all lines across the entire memory array. This local optimization reduces the harmful coupling effect while maintaining access capability.
Data Source
AI summary
Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between the transistor and the memory cells. Other embodiments including additional apparatus and methods are described.