Semiconductor Device Manufacturing with Variable-Thickness Resist Mask
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Solution Overview
Problem
The existing methods for manufacturing semiconductor devices with LDD and GOLD structures are complex and require multiple photolithography processes, leading to increased complexity and potential damage to the gate insulating layer during impurity injection.
Innovation Solution
A method involving the formation of resist patterns with varying thicknesses to allow for simultaneous etching and impurity injection, reducing the number of photolithography processes and ensuring self-alignment of impurity regions without damaging the gate insulating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photolithography processes are used to form LDD and GOLD structures, then the manufacturing precision of impurity regions is improved, but the device complexity and manufacturing time increase
Solution Approach 1:
The patent combines multiple photolithography processes into a single process by using a photomask with multiple regions having different light transmittance. This allows simultaneous formation of heavily doped and lightly doped impurity regions in one exposure step, reducing process complexity while maintaining precision through the differentiated transmittance regions of the mask
Solution Approach 2:
The photomask is designed to serve multiple functions simultaneously: it defines both heavily doped and lightly doped region boundaries, controls impurity diffusion patterns, and enables self-alignment of multiple impurity regions. This multi-functional mask eliminates the need for separate photolithography steps for each impurity region
2Manufacturing precision
If dry etching is used to control gate electrode film thickness, then the manufacturing precision of gate electrode is improved, but the ease of manufacture decreases due to material selection limitations
Solution Approach 1:
The patent changes the control parameter for gate electrode thickness from etching depth (in dry etching) to photoresist thickness (in photolithography). By controlling the thickness of the photoresist layer, the gate electrode thickness is precisely controlled during the impurity injection process, allowing broader material selection and simpler manufacturing without the constraints of dry etching selectivity ratios
3Ease of manufacture
If impurity injection is performed through gate insulating layer, then the ease of manufacture is improved, but the reliability of gate insulating layer decreases due to potential damage
Solution Approach 1:
The patent performs preliminary action by forming the gate insulating layer and gate electrode structure before impurity injection. The photoresist is then applied over this completed structure, and impurities are injected through the photoresist rather than through the gate insulating layer. This preliminary structuring protects the gate insulating layer from direct impurity exposure while maintaining manufacturing efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces the number of photolithography steps, and enhances the reliability and insulating properties of the gate insulating layer, while achieving specific electrical characteristics for the semiconductor device.
Implementation Method 1
forming the heavily doped source region and the heavily doped drain region by etching the semiconductor film in a predetermined pattern using the resist as a mask
Implementation Method 2
a gate electrode opposite to the semiconductor layer with an insulating layer interposed therebetween
Data Source
AI summary
The present invention is directed to a method of manufacturing a semiconductor device including a semiconductor layer having a heavily doped source region, a heavily doped drain region, a lightly doped source region, a lightly doped drain region and a channel region, and a gate electrode opposite to the semiconductor layer with an insulating layer interposed therebetween. The method includes forming a semiconductor film on a substrate, forming a resist on the semiconductor film such that a first portion of the resist corresponding to the heavily doped source region and the heavily doped drain region is thinner than a second portion of the resist corresponding to the lightly doped source region, the lightly doped drain region and the channel region. In addition, the method includes forming the heavily doped source region and the heavily doped drain region by etching the semiconductor film in a predetermined pattern using the resist as a mask and injecting high density impurities into the semiconductor film through the first portion of the resist, removing the resist from the semiconductor film to form a gate insulating layer on the semiconductor film. Further, the method includes forming the gate electrode at a position on the gate insulating layer which corresponds to the channel region, and forming the lightly doped source region and the lightly doped drain region by injecting impurities having a density lower than the density of the high density impurities into the semiconductor film using the gate electrode as a mask.