Vertical Transistor Resistive Memory Cell Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional resistive memory devices face challenges in scaling down due to issues with current drivability and punch-through current leakage as feature sizes shrink, limiting the ability to reduce memory cell size effectively.
Innovation Solution
The implementation of an array of vertical selection transistors with a semiconductor pillar structure and a gate electrode configuration that allows for a wider and longer conductive channel, reducing the memory cell size to 4F^2 while mitigating short channel and current drivability issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistors are used with scaled-down feature sizes, then device density is improved, but current drivability deteriorates and punch-through leakage increases
Solution Approach 1:
The patent transitions from conventional planar transistors to vertically-standing transistors, utilizing the third dimension (vertical orientation) to achieve longer channel lengths and wider effective channel widths without increasing the lateral footprint. This dimensional change allows the transistor channel to extend perpendicular to the substrate surface, enabling better current control and drivability while maintaining high device density.
Solution Approach 2:
The vertically-standing transistor structure nests multiple functional regions (source, drain, channel, gate) within a compact vertical architecture. The gate electrode wraps around or surrounds the channel region, creating a nested configuration where the gate controls the channel from multiple sides, improving electrostatic control and current drivability within a small lateral space.
2Area of stationary object
If conventional planar transistors are scaled down to smaller feature sizes, then cell size is reduced, but punch-through current leakage increases
Solution Approach 1:
By standing the transistor vertically, the channel length is extended in the vertical dimension rather than being constrained to the lateral plane. This allows for longer effective channel lengths that provide better electrostatic control over the charge carrier flow, preventing punch-through leakage even when the lateral cell dimensions are scaled down to minimal sizes.
Solution Approach 2:
The vertical transistor architecture introduces asymmetry in the spatial distribution of electrostatic control, with the gate positioned to maximize its control over the vertical channel. This asymmetric configuration creates stronger electric field control that prevents carrier punch-through from source to drain, addressing the leakage issue while maintaining compact lateral dimensions.
3Ease of manufacture
If conventional planar transistors are used, then manufacturing process is simpler, but device density is limited
Solution Approach 1:
The vertical transistor structure utilizes vertical stacking and three-dimensional electrode arrangements to achieve higher device density. By extending the transistor channel vertically and arranging source, drain, and gate electrodes in three-dimensional space, the design packs more functional elements into the same lateral footprint, increasing overall device density while using extended manufacturing techniques.
Data Source
AI summary
The present invention relates to resistive memory devices incorporating therein vertical selection transistors and methods for making the same. A resistive memory device comprises a semiconductor substrate having a first type conductivity; a plurality of vertical selection transistors formed on the semiconductor substrate in an array, each of the plurality of vertical selection transistors including a semiconductor pillar protruded from the semiconductor substrate, top region of the semiconductor pillar having a second type conductivity opposite to the first type conductivity provided in the semiconductor substrate; and a gate electrode surrounding the semiconductor pillar with a gate dielectric layer interposed therebetween, the gate electrode being lower in height than the semiconductor pillar; a plurality of contact studs disposed on top of the vertical selection transistors; a plurality of resistive memory elements disposed on top of the contact studs; a plurality of parallel word lines connecting the vertical selection transistors by way of respective gate electrodes, the parallel word lines extending along a first direction; a plurality of parallel bit lines connecting the resistive memory elements, the parallel bit lines extending along a second direction different from the first direction provided in the parallel word lines; and a plurality of parallel source lines with the second type conductivity formed in top regions of the semiconductor substrate in between rows of the semiconductor pillars, wherein the source lines and the top regions of the semiconductor pillars function as source and drain, respectively.