TFT Array Substrate Shared Electrode Structure
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Solution Overview
Problem
In TFT array substrates, the overlap of the storage capacitor area with the insulator layer results in a thick structure, leading to decreased capacitance and increased parasitic capacitance, which affects image display quality.
Innovation Solution
The TFT array substrate design includes a shared electrode and etching stop layer structure, where the storage capacitor is formed by sequentially stacking the first electrode layer, etching stop layer, and second electrode layer, allowing the insulation layer to be etched simultaneously with the driving circuit area, thereby increasing capacitance and reducing parasitic capacitance without additional photolithography processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the storage capacitor area overlaps with the gate insulator layer, then the area utilization is improved, but the parasitic capacitance increases affecting image display quality
Solution Approach 1:
The storage capacitor is extracted from the overlapping region with the gate insulator layer and placed in a dedicated storage capacitor area. This extraction eliminates the source of parasitic capacitance while the capacitor maintains its essential function through proper electrode and dielectric layer configuration.
2Manufacturing precision
If separate etching processes are used for the insulation layer in the storage capacitor area, then the manufacturing precision is improved, but the device complexity and manufacturing time increase
Solution Approach 1:
The etching process for the gate insulator layer in the TFT area and the insulation layer in the storage capacitor area are merged into a single simultaneous etching operation. The shared etching stop layer enables this unified process while maintaining the precision required for both areas, reducing manufacturing steps and complexity.
Solution Approach 2:
The etching stop layer serves multiple functions: it protects underlying layers during etching, defines etching boundaries, and enables simultaneous processing of different areas. This multi-functionality allows a single etching process to achieve what would otherwise require separate specialized processes.
Data Source
AI summary
A TFT array substrate is disclosed. The TFT array substrate includes a TFT area, which includes a TFT first electrode layer, a TFT second electrode layer, a TFT insulation layer, and a TFT etching stop layer. The TFT array substrate also includes also includes a storage capacitor, which includes a capacitor first electrode layer, a capacitor second electrode layer, a capacitor insulation layer, and a capacitor etching stop layer. The TFT first electrode layer and the capacitor first electrode layer are formed in a shared first electrode layer, the TFT second electrode layer and the capacitor second electrode layer are formed in a shared second electrode layer, the TFT insulation layer and the capacitor insulation layer are formed in a shared insulation layer, and the TFT etching stop layer and the capacitor etching stop layer are formed in a shared etching stop layer.