CMOS Wafer Hydrogen Venting via Dielectric Barrier Openings

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Solution Overview

Problem

Positive bias temperature instability (PBTI) in MOS transistors leads to threshold voltage shifts, causing decreased drive current and potential device failure, especially in larger integrated circuit dies where hydrogen diffusion is not effectively vented due to the lateral extent exceeding a critical size.

Innovation Solution

Incorporating a silicon nitride/silicon oxynitride bilayer dielectric barrier layer with strategically placed annular and peripheral openings to enhance hydrogen out-diffusion, reducing PBTI effects by providing sufficient venting areas within the dielectric stack.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the die size is increased to accommodate more transistors and interconnect layers, then the transistor density and circuit functionality are improved, but the hydrogen diffusion path length increases causing PBTI effects to worsen

Engineering Contradiction:
Improvetransistor densityVSAvoiddevice stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent divides the die into multiple hydrogen venting zones by placing multiple openings in the dielectric barrier layer at different locations. Each opening serves a local region, ensuring that hydrogen diffusion distance from any point on the die to the nearest opening remains within the critical threshold. This segmentation allows large dies to maintain effective hydrogen venting while accommodating high transistor density.

Inventive Principle:
Principle #1Segmentation

2Reliability

If a continuous dielectric barrier layer is used to prevent hydrogen diffusion, then PBTI protection is improved, but hydrogen venting capability deteriorates

Engineering Contradiction:
ImprovePBTI protectionVSAvoidhydrogen accumulation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by creating openings in the dielectric barrier layer at specific strategic locations rather than making the barrier continuous. The openings are placed based on hydrogen generation sources (such as near scribe seals and in regions with high hydrogen production from dielectric deposition), allowing the barrier to maintain its protective function in most areas while providing localized venting paths where hydrogen accumulation would be most problematic.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces PBTI-related threshold voltage shifts, maintaining device stability and performance by ensuring hydrogen is adequately removed from the dielectric stack, even in larger dies, thereby preventing device failure.

Implementation Method 1

A dielectric barrier layer is located between the ILD layer and the metal electrode

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Implementation Method 2

strategically placed annular and peripheral openings to enhance hydrogen out-diffusion

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS10886120B2Hydrogen ventilation of CMOS wafers
Publication Date: 2021.01.05 TEXAS INSTRUMENTS INC
  • US10886120B2 patent drawing
  • US10886120B2 patent drawing
  • US10886120B2 patent drawing

AI summary

An integrated circuit a semiconductor substrate includes a device die with includes transistors configured to execute an electrical function. A first interconnect layer of the device die is configured to route electrical signals or power to terminals of the transistors. An interlevel dielectric (ILD) layer is located over the interconnect layer. A metal electrode located over the ILD layer. A dielectric barrier layer is located between the ILD layer and the metal electrode. A scribe seal surrounds the device die. A first opening within the dielectric barrier layer surrounds the metal electrode. Second and third openings within the dielectric barrier layer are located between the first opening and the scribe seal.