Shared Select Gates for Memory Cell Density
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Solution Overview
Problem
As memory cell density increases for a given device area, producing memory devices that meet performance preferences becomes challenging due to the complexity of managing select gates and transistors in memory arrays.
Innovation Solution
The implementation of memory devices with shared select gates, such as shared bottom source select gates or shared top drain select gates, allows for efficient coupling and decoupling of memory cell strings during read or write operations, improving memory cell density by reducing leakage current and enhancing the on-to-off current ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased for a given device area, then more memory cells can be stored, but performance preferences become difficult to meet due to complexity of managing select gates and transistors
Solution Approach 1:
Multiple select transistors share a common gate structure, merging control functions to reduce the number of independent gate management circuits. This allows higher memory cell density while reducing the complexity overhead associated with managing individual select gates for each transistor.
Solution Approach 2:
The common gate structure serves multiple select transistors simultaneously, making it a universal control element that manages multiple memory cell strings. This multi-functionality reduces the overall complexity of gate management while enabling increased memory cell density.
2Quantity of substance
If more memory cells are coupled to each data line, then memory cell density increases, but leakage current management becomes more challenging
Solution Approach 1:
Multiple select transistors share a common gate, merging their control functions. This reduces the total number of gate structures and associated leakage paths, allowing more memory cells to be coupled to each data line while managing leakage current effectively.
Solution Approach 2:
The patent extracts and eliminates redundant gate structures by implementing shared gates. This removal of unnecessary components reduces leakage current while maintaining the ability to couple more memory cells to each data line.
Data Source
AI summary
Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select transistor coupled to the memory cell string. In at least one of such apparatuses, the select transistor can include a body region including a monocrystalline semiconductor material. Other embodiments including additional apparatuses and methods are described.