Vertical Pillar Semiconductor Device With Stress Providing Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current electronic charge-controlled devices face limitations in developing next-generation memory devices with high capacity, ultra-high speed, and ultra-low power consumption, particularly in improving integration density and maintaining high resistance variable characteristics in resistive memory devices.
Innovation Solution
A semiconductor device with a vertical channel structure is developed, featuring a pillar extending perpendicular to the substrate, a stress providing layer for lattice deformation, source and drain regions, and a gate electrode surrounding the pillar, which enhances carrier mobility by applying tensile stress to the channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional transistor structure with vertical channel is employed to improve integration density, then more memory cells can be integrated in a limited area, but high operation current is required to maintain high resistance variable characteristics
Solution Approach 1:
The patent changes the physical state and properties of the channel material by introducing a stress providing layer that applies tensile stress to the semiconductor layer. This stress induces lattice deformation and increases carrier mobility, allowing the device to achieve high resistance variable characteristics with lower operation current while maintaining the 3D vertical channel structure for high integration density
Solution Approach 2:
The patent uses a composite structure consisting of a semiconductor layer forming the channel and a stress providing layer with different lattice constant. This composite material system creates beneficial mechanical stress that enhances carrier mobility in the channel, enabling the device to overcome the high current requirement issue while maintaining the space-efficient 3D architecture
2Quantity of substance
If the channel length is reduced to increase integration density, then more memory cells fit in limited area, but carrier mobility and resistance control become more difficult
Solution Approach 1:
The patent applies mechanical stress as a controlling parameter to enhance carrier mobility in the shortened channel. The stress providing layer creates tensile stress that deforms the crystal lattice, increasing carrier velocity and maintaining effective channel performance even when the physical channel length is reduced for higher integration density
Solution Approach 2:
The patent transitions from controlling device performance primarily through channel length (one dimension) to utilizing stress-induced lattice deformation (adding a mechanical dimension). This allows the device to achieve good resistance variable characteristics with shorter channels by controlling the stress state rather than relying solely on channel dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution increases carrier mobility and integration density, enabling the development of high-capacity, high-speed, and low-power resistive memory devices with improved resistance variable characteristics.
Implementation Method 1
a stress providing layer formed over a lower side wall of the pillar, wherein the stress providing layer is suitable to cause lattice deformation in the pillar
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a first conductivity type, a plurality of pillars extending to a direction perpendicular to a surface of the semiconductor substrate, a stress providing layer formed in the semiconductor substrate between pillars and forming a junction with the semiconductor substrate below each pillar to cause lattice deformation in the pillar, a source region having a second conductivity type opposite to the first conductivity type formed in the semiconductor substrate below the pillar, a drain region having the second conductivity type formed in an upper portion of the pillar, a gate insulating layer formed on a lateral surface of the pillar and a surface of the stress providing layer, and a gate electrode formed to surround the lateral surface of the pillar.