Semiconductor Memory Device with Laminated Volatile and Non-Volatile Areas
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Solution Overview
Problem
Current laminated NAND flash memory devices have insufficient integration of peripheral circuits, which hinders the improvement of bit density and efficiency in non-volatile semiconductor memory devices.
Innovation Solution
A semiconductor memory device is designed with a combination of non-volatile and volatile memory areas, where volatile memories are used as latch circuits and sense amplifiers, and a laminated structure is implemented to integrate these components efficiently, allowing for improved data storage and retrieval operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a laminated NAND flash memory structure is used to improve bit density, then storage capacity increases, but peripheral circuit integration remains insufficient
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking by implementing memory cells in multiple layers stacked above a substrate. This dimensional change allows significant increase in bit density while providing sufficient space for peripheral circuits to be integrated in the horizontal plane, thus resolving the contradiction between storage capacity and circuit integration.
Solution Approach 2:
The patent combines non-volatile memory cells and volatile memory cells into a single laminated structure, where both types of memory cells share common components such as bit lines and word lines. This merging approach increases overall storage capacity while reducing the complexity of peripheral circuits by eliminating redundant structures.
2Productivity
If volatile memories are used as latch circuits and sense amplifiers, then data handling efficiency improves, but device area increases
Solution Approach 1:
The patent merges volatile memory cells with latch circuits and sense amplifiers into a single integrated structure. The volatile memory cells are positioned adjacent to the non-volatile memory cells and share common bit lines and word lines, eliminating the need for separate latch and sense amplifier circuits. This merging approach improves data handling efficiency while minimizing device area.
Solution Approach 2:
The patent designs the volatile memory cells to serve multiple functions: they act as both storage elements and as latch circuits/sense amplifiers for the non-volatile memory cells. This multi-functionality approach enables improved data handling efficiency without requiring additional dedicated circuits, thus avoiding increase in device area.
Data Source
AI summary
A volatile memory area includes a plurality of second memory cells, a third select transistor, and a fourth select transistor. The plurality of second memory cells are electrically connected in series, and stacked above the substrate. The third select transistor is connected to one end of the plurality of second memory cells, and connected to a second bit line. The fourth select transistor is connected to the other end of the plurality of second memory cells, and unconnected to a second source line. A controller is configured to supply a first voltage to all gates of the second memory cells. The first voltage is capable of turning on the plurality of second memory cells.