Semiconductor Contact Holes via Insulating Fences
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Solution Overview
Problem
In semiconductor device fabrication, particularly for DRAM devices with line widths less than 80 nm, conventional methods face challenges in preventing photoresist deformation, achieving vertical etch profiles, and avoiding electric shorts and insulation degradation during the formation of contact holes with high aspect ratios and stacked structures.
Innovation Solution
The method involves forming a first inter-layer insulation layer, selectively etching to create contact holes, removing etch residues, depositing insulating fences on the inner walls, forming bit lines, and then selectively etching a second inter-layer insulation layer to create storage node contact holes, while using insulating fences to prevent electric shorts and maintaining insulation properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to form contact holes with high aspect ratios, then the contact holes can be formed, but photoresist deformation occurs and vertical etch profile cannot be maintained
Solution Approach 1:
A mandrel structure is introduced as an intermediary element to enable self-aligned contact hole formation. The mandrel serves as a sacrificial template that defines the contact hole position and shape, allowing the etch process to proceed without photoresist deformation while maintaining vertical profile. The mandrel is removed after etching, leaving precisely defined contact holes.
Solution Approach 2:
The mandrel structure is formed in advance before the contact hole etching process. This preliminary structure preparation enables the subsequent etching to proceed with proper alignment and profile control, preventing photoresist deformation by eliminating the need for traditional photoresist coating and patterning steps.
2Ease of manufacture
If contact holes are formed without insulating fences, then the fabrication process is simpler, but electric shorts occur between bit line contacts
Solution Approach 1:
Insulating fences are formed as intermediary structures between bit line contacts to prevent electric shorts. These fences act as isolation barriers that electrically separate adjacent contacts while maintaining the overall structural integrity. The fences are integrated into the fabrication process without significantly complicating the manufacturing steps.
3Reliability
If cleaning processes are performed to remove etch residues, then contact resistance is reduced, but seams are generated on contact hole walls
Solution Approach 1:
The mandrel structure is removed in advance before the cleaning process that removes etch residues. This preliminary removal prevents the cleaning chemicals from attacking the contact hole walls and creating seams. The mandrel removal is performed using a selective process that does not damage the contact hole structure.
4Adaptability or versatility
If device elements are formed in stacks to increase integration level, then more functions are achieved, but alignment precision and etching control become more difficult
Solution Approach 1:
The mandrel structure serves as a mediator that enables precise alignment in stacked device configurations. By using the mandrel as a self-aligned template, the contact holes are automatically positioned with high precision relative to the stacked elements, eliminating the need for additional alignment steps and maintaining manufacturing precision despite increased integration complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents electric shorts between bit line contacts, maintains insulation integrity, and reduces the risk of seam generation, thereby improving the yield and reliability of semiconductor devices.
Implementation Method 1
selectively etching the first inter-layer insulation layer to form a plurality of first contact holes
Implementation Method 2
performing a cleaning process to remove etch residues on lower portions of the first contact holes
Implementation Method 3
depositing insulating fences on the inner walls
Data Source
AI summary
Disclosed is a method for fabricating a semiconductor device. The method includes: forming a first inter-layer insulation layer on a substrate provided with a plurality of cell contact plugs; selectively etching the first inter-layer insulation layer to form a plurality of first contact holes; performing a cleaning process to remove etch residues on lower portions of the first contact holes; forming insulating fences on inner walls of the first contact holes; forming a plurality of bit lines in contact with a group of the cell contact plugs through the respective first contact holes; forming a second inter-layer insulation layer over the plurality of bit lines; planarizing the second inter-layer insulation layer until an upper portion of each of the bit lines is exposed; and selectively etching the second inter-layer insulation layer in alignment with the bit lines, thereby obtaining a plurality of second contact holes.