3D NAND Stack Structure With Reduced Sacrificial Layers
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Solution Overview
Problem
There is a need for semiconductor devices with increased data storage capacity and improved reliability in data storage systems.
Innovation Solution
A semiconductor device design featuring first and second regions with specific stack and mold structures, including gate and sacrificial layers, channel structures, and alignment structures, optimized to enhance data storage capacity and reliability by reducing the number of horizontal sacrificial layers relative to gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of horizontal sacrificial layers is increased to match the number of gate electrodes, then the structural completeness is improved, but the manufacturing complexity and defect risk increase
Solution Approach 1:
The patent extracts and removes certain horizontal sacrificial layers from the mold structure, specifically making the number of lower horizontal sacrificial layers less than the number of lower gate electrodes. This selective removal simplifies the manufacturing process while maintaining the essential structural support needed for reliable device operation.
2Manufacturing precision
If more sacrificial layers are used, then the pattern formation accuracy is improved, but the manufacturing time and process steps increase
Solution Approach 1:
The patent applies partial action by using a reduced number of horizontal sacrificial layers compared to the total number of gate electrodes. This partial configuration is sufficient to achieve the required pattern formation accuracy without the need for excessive sacrificial layers, thereby optimizing manufacturing efficiency.
3Volume of moving object
If the distance between gate electrodes and channel structures is reduced, then the device density is improved, but the alignment precision requirements increase
Solution Approach 1:
The patent addresses alignment precision by controlling the vertical distance in the first direction between the uppermost lower gate electrode and the upper end of the first channel structure. This dimensional control ensures proper alignment while maintaining reduced device volume, as the horizontal spacing can be minimized without compromising vertical alignment accuracy.
Data Source
AI summary
A semiconductor device includes a substrate having first and second regions; a first stack structure including lower gate electrodes stacked in a first direction in the first region; a first channel structure penetrating through the first stack structure; a second stack structure on the first stack structure and the first channel structure and including upper gate electrodes stacked in the first direction; a second channel structure penetrating through the second stack structure; a first mold structure including lower horizontal sacrificial layers stacked in the second region; an alignment structure penetrating through the first mold structure; and a second mold structure on the first mold structure and the alignment structure and including upper horizontal sacrificial layers stacked, wherein the number of the lower horizontal sacrificial layers is less than the number of the lower gate electrodes.