3D NAND Memory Reset Read Operation for Voltage Control
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Solution Overview
Problem
Three-dimensional (3D) NAND memory devices face challenges with widening threshold voltage distribution and increased bit error rate due to re-read triggers, which impact system performance and data integrity, necessitating improved read window budget and threshold voltage control.
Innovation Solution
A reset read operation is introduced to maintain 3D NAND memory cells in a transient state, ensuring a tight cell threshold voltage distribution and wide read window budget, reducing re-read triggers, and optimizing power consumption by executing the operation on multiple blocks concurrently or automatically after an erase operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D NAND memory devices are used to increase memory cell density, then storage capacity is improved, but threshold voltage distribution widens and bit error rate increases
Solution Approach 1:
The patent applies preliminary action by performing a reset read operation before the actual read operation. This reset read sets the memory cells to a known transient state, ensuring that the threshold voltage distribution is tight and the read window budget is maximized before data is read, thereby preventing bit errors that would otherwise occur due to voltage drift in high-density 3D NAND structures
2Speed
If conventional read operations are performed without reset, then read speed is maintained, but read window budget decreases and re-read triggers increase
Solution Approach 1:
The reset read operation is performed as a preliminary action before the actual read operation. This preliminary step sets the memory cells to a transient state with optimized threshold voltage distribution, ensuring a wide read window budget is available when the actual read occurs, thereby maintaining both speed and reliability
Solution Approach 2:
The reset read operation is performed periodically or automatically after erase operations and before read operations. This periodic resetting ensures that memory cells are consistently maintained in an optimal transient state, preventing threshold voltage drift and eliminating the need for re-read triggers while maintaining high read speeds
3Reliability
If reset read operation is performed on all blocks, then threshold voltage distribution is optimized, but power consumption increases
Solution Approach 1:
The patent applies local quality by performing the reset read operation selectively on only those memory blocks that require it, rather than uniformly on all blocks. This targeted approach optimizes threshold voltage distribution in specific blocks where needed while minimizing unnecessary power consumption in blocks that are already in an acceptable state, achieving a balance between reliability and energy efficiency
Data Source
AI summary
Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.