3D NAND Select Gate Fabrication via Preliminary Deposition
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Solution Overview
Problem
The existing fabrication techniques for three-dimensional NAND memory structures are time-consuming and costly due to the additional steps required for forming select gate layers after the deposition of channel layers, which also affect the uniformity and reliability of the channel film layer.
Innovation Solution
The method involves depositing the select gate layer immediately after the alternating conductive and dielectric layers, followed by the deposition of sacrificial material in hollow channels, which is then selectively removed to expose and remove the upper film layer, allowing for a continuous and uniform channel film layer to be deposited, thereby reducing production time and cost while improving consistency and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the select gate layer is formed after the channel layer deposition using existing fabrication techniques, then the select gate functionality is achieved, but the production time and cost increase due to additional fabrication steps
Solution Approach 1:
The select gate layer is deposited in advance during the initial alternating conductive and dielectric layer formation, before the hollow channels are created. This preliminary placement of the select gate layer eliminates the need for subsequent select gate formation steps, directly reducing production time while maintaining functionality
Solution Approach 2:
The select gate layer formation is merged with the initial stack formation process. By depositing the select gate layer simultaneously with the conductive and dielectric layers during the original lamination process, multiple structural elements are created in a single fabrication sequence, improving productivity
2Reliability
If the select gate layer is formed after the channel layer deposition, then the select gate structure is created, but the uniformity and smoothness of the channel film layer deteriorates
Solution Approach 1:
The select gate layer is positioned in advance during stack formation, allowing the channel layer to be deposited as a continuous, uniform film over a pre-prepared surface. This prevents disruptions to channel layer uniformity that would occur if the select gate were formed afterward
Solution Approach 2:
The select gate layer is strategically positioned only at specific locations (drain-end and source-end) before channel deposition, allowing the channel layer to maintain high uniformity in critical regions while the select gate provides localized functionality where needed
3Reliability
If additional fabrication steps are added for select gate formation, then the select gate functionality is improved, but the production cost increases
Solution Approach 1:
The select gate layer formation is combined with the initial stack formation process, eliminating the need for separate select gate fabrication steps. This merging of operations reduces equipment usage, material consumption, and labor costs while maintaining select gate functionality
Solution Approach 2:
The initial alternating conductive and dielectric layer deposition process serves multiple functions: it creates both the select gate layers and the structural framework for the 3D NAND device. This multi-functionality reduces the total number of specialized fabrication steps required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces production time and cost, enhances the uniformity and smoothness of the channel film layer, and improves the topmost word line trap-to-band tunneling between the select gate and the cell, leading to improved 3D NAND memory performance.
Implementation Method 1
selectively removing the sacrificial material to a first defined depth measured from the first end of each of the plurality of hollow channels, the selective removal of the sacrificial material exposing an upper film layer included in the plurality of film layers
Implementation Method 2
selectively removing at least the exposed upper film layer included in the plurality of film layers to the first defined depth
Data Source
AI summary
A 3D NAND storage device includes a plurality of layers containing doped semiconductor material interleaved with a plurality of layers of dielectric material. Each of the pillars forming the 3D NAND storage device includes a plurality of memory cells and a drain-end select gate (SGD). The pillars are separated by a hollow channel in which a plurality of film layers, including at least a lower film layer and an upper film layer have been deposited. The systems and methods described herein remove at least the upper film layer proximate the SGD while maintaining the film layers proximate the memory cells. Such an arrangement beneficially permits tailoring the film layers proximate the SGD prior to depositing the channel film layer in the hollow channel. The systems and methods described herein permit the deposition of a continuous channel film layer proximate both the memory cells and the SGD.