3D NAND Select Gate Segmentation for Compute-in-Memory Parallelism
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The classical von Neumann computing architecture is limited by high power consumption and processing speed due to frequent data migration between memory and processor, and its bandwidth constraints hinder performance improvement, especially in big data and artificial intelligence applications.
Innovation Solution
A semiconductor device with a stack structure and select gate layer divided by isolating structures, allowing parallel application of input voltages to select gates for improved input parallelism and operation efficiency, incorporating a three-dimensional NAND type memory for compute-in-memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred between memory and processor through a data bus in von Neumann architecture, then data processing can be performed, but power consumption increases and processing speed decreases due to frequent data migration
Solution Approach 1:
The patent merges the memory and processor functions by implementing select gates directly within the memory stack structure. The select gate layer is integrated with the memory cell stack, allowing computation to be performed at the location where data is stored, thereby eliminating the need for frequent data transfer between separate memory and processor components.
Solution Approach 2:
The patent transitions from a two-dimensional planar architecture to a three-dimensional vertical stack structure. The select gate layer is positioned vertically above the memory cell stack along the first direction, enabling parallel control of multiple memory cells through the isolating structures that divide the select gate layer into multiple rows and columns.
2Productivity
If memory bandwidth is limited, then memory can be implemented, but processor processing speed is limited by memory access speed
Solution Approach 1:
The select gate layer is segmented into multiple select gate rows and columns through isolating structures. This segmentation allows independent control of different regions of the memory stack, enabling parallel access to multiple memory cells simultaneously, thereby increasing the effective memory bandwidth and processing speed.
Solution Approach 2:
The select gate layer serves multiple functions: it acts as both a selection mechanism for accessing specific memory cells and as a control element for parallel operations. The same select gate infrastructure enables both data retrieval and computation operations, improving overall system throughput.
3Productivity
If select gate layer is divided into multiple select gate rows and columns using isolating structures, then input parallelism is improved, but device complexity increases
Solution Approach 1:
The isolating structures are nested within the existing memory stack fabrication process. The first and second select gate isolating structures are formed as part of the sequential layer deposition process, where each isolating structure is deposited between specific conductive and insulating layers, integrating the segmentation function without requiring separate complex fabrication steps.
Solution Approach 2:
The isolating structures are formed in advance during the stack fabrication process before the memory cells are fully operational. By pre-positioning the isolating structures that define the select gate rows and columns, the patent enables parallel input capability from the outset without requiring additional complex post-processing steps.
Data Source
AI summary
Semiconductor devices, systems, and operating methods thereof are provided. An example semiconductor device includes: a stack structure including conductive layers and insulating layers stacked alternately along a first direction, a select gate layer located on the stack structure along the first direction, first select gate isolating structures penetrating through the select gate layer along the first direction, and second select gate isolating structures penetrating through the select gate layer along the first direction. A first select gate isolating structure divides the select gate layer into a plurality of select gate rows arranged along a second direction, and a second select gate isolating structure divides one or more select gate rows into a plurality of first select gates arranged along a third direction. The second direction intersects with the third direction, and the second direction and the third direction are both perpendicular to the first direction.