3D NAND Memory Selective Plane Activation
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Solution Overview
Problem
Increasing memory capacity in 3D memory devices through vertical channel structures leads to increased capacitance, noise, and power consumption due to the higher density of conductive lines, which complicates manufacturing processes.
Innovation Solution
A memory device architecture that uses multiple conductive lines, including block select lines, layer select lines, and string select lines, to selectively activate specific stacks and layers of conductive strips, reducing the need for increased horizontal conductive strips and minimizing trade-offs in memory capacity, capacitance, and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacks of horizontal conductive strips is increased to increase memory capacity, then memory capacity is improved, but capacitance, noise, and power consumption increase
Solution Approach 1:
The patent divides the memory array into multiple planes, with each plane containing a subset of the total stacks. This segmentation allows selective activation of only the necessary planes and stacks for each memory operation, rather than having all stacks continuously active. The conductive lines are organized into plane-specific groups, enabling independent control of each plane's power consumption.
Solution Approach 2:
The patent introduces a third dimension by stacking multiple planes vertically, where each plane contains a portion of the memory stacks. This 3D arrangement allows the memory capacity to be increased by adding more planes rather than simply increasing the number of stacks in a single plane, thereby distributing the capacitance and power load across multiple separated planes.
2Quantity of substance
If the number of stacks of horizontal conductive strips is increased to increase memory capacity, then memory capacity is improved, but noise increases
Solution Approach 1:
By segmenting the memory into multiple planes with separate conductive line sets for each plane, the patent isolates the noise generated by each plane. When only specific planes are active, the noise from inactive planes is minimized, and the noise from active planes is contained to their respective conductive line groups rather than affecting the entire memory array.
3Quantity of substance
If the number of planes and staircase contacts is increased to increase memory capacity, then memory capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the conductive lines into plane-specific groups, where each plane has its own dedicated set of conductive lines for accessing its stacks. This segmentation simplifies the manufacturing process by allowing each plane to be addressed independently, reducing the complexity of routing and connecting conductive lines compared to a fully interconnected architecture.
4Quantity of substance
If more conductive lines are used to access more stacks, then memory capacity is improved, but capacitance increases
Solution Approach 1:
By organizing conductive lines into plane-specific groups and enabling selective plane activation, the patent ensures that only the capacitance associated with the currently active plane's conductive lines is fully utilized. Inactive planes' conductive lines remain dormant, effectively reducing the total active capacitance compared to an architecture where all conductive lines must be continuously managed.
Data Source
AI summary
A memory device includes a plurality of stacks of conductive strips, a plurality of conductive vertical structures arranged orthogonally to the plurality of stacks, memory elements in interface regions at cross-points between side surfaces of the plurality of stacks and the plurality of conductive vertical structures, multiples pluralities of conductive lines, and control circuitry. The plurality of stacks of conductive strips alternate with insulating strips, including at least a bottom layer of conductive strips, a plurality of intermediate layers of conductive strips, and a top layer of conductive strips. A first plurality of conductive lines electrically couple to the top layer of the conductive strips. A second plurality of conductive lines and a third plurality of conductive lines electrically couple to the plurality of intermediate layers. The control circuitry causes the first plurality of conductive lines to select at least a first particular stack in the plurality of stacks, the second plurality of conductive lines to select at least the first particular stack in the plurality of stacks, and the third plurality of conductive lines to select at least one particular layer in the plurality of intermediate layers.