3D NAND Sensor Device Wafer Bonding Yield
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing method of stacking three chips (DRAM, pixel, and ISP) in CMOS image sensors for increased storage capacity has low manufacturing yield and limited storage capacity due to dimensional constraints, failing to meet demands for larger storage and higher data processing speed.
Innovation Solution
A sensor device and manufacturing method involving a first wafer structure with an integrated circuit layer and 3D NAND memory cell array bonded to a second wafer structure with a sensing module, using advanced semiconductor processes to enhance yield and capacity without increasing dimensions, replacing DRAM with SRAM and incorporating a 3D NAND memory module.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three chips (DRAM, pixel, and ISP) are stacked and bonded to increase storage capacity, then storage capacity is improved, but manufacturing yield deteriorates due to complex three-dimensional bonding processes
Solution Approach 1:
The patent merges the DRAM chip and pixel chip into a single integrated structure where the pixel chip is formed directly on the DRAM chip substrate. This integration eliminates the need for separate bonding processes between three chips, reducing process complexity and improving manufacturing yield while maintaining increased storage capacity through the combined structure.
Solution Approach 2:
The pixel chip structure is designed to serve multiple functions: it provides imaging functionality while also serving as additional storage capacity. By making the pixel chip multi-functional (both sensing and storage), the system reduces the number of separate components needed, simplifying the bonding process and improving manufacturing yield.
2Adaptability or versatility
If the dimension of the DRAM chip is made the same as the pixel chip and ISP chip, then device compatibility is improved, but storage capacity is limited and cannot meet demands for larger storage
Solution Approach 1:
The patent transitions from two-dimensional planar expansion to three-dimensional vertical integration. By stacking the pixel chip on top of the DRAM chip substrate and utilizing vertical space for memory cell arrays, the system achieves larger storage capacity without increasing the lateral dimensions, thereby maintaining device compatibility while exceeding storage requirements.
Solution Approach 2:
The patent implements a nested structure where the pixel chip is positioned on the DRAM chip substrate, and memory cell arrays are embedded within the vertical structure. This nesting allows multiple functional layers to occupy the same lateral footprint, increasing storage capacity without expanding device dimensions and preserving compatibility with standard device form factors.
3Quantity of substance
If three chips are stacked for increased storage, then storage capacity is improved, but device complexity increases due to multiple bonding interfaces
Solution Approach 1:
The patent combines the DRAM chip and pixel chip into a single integrated device with unified bonding interfaces. By merging these components during the fabrication process rather than bonding separate finished chips, the system reduces the number of bonding interfaces from multiple chip-to-chip connections to a single integrated structure, thereby reducing device complexity.
4Ease of manufacture
If DRAM chip dimension is constrained to match pixel and ISP chips, then manufacturing compatibility is improved, but data processing speed and storage capacity demands cannot be satisfied
Solution Approach 1:
The patent addresses the limitation of constrained chip dimensions by utilizing the vertical dimension for expanding memory capacity and processing capability. The 3D stacked architecture allows larger effective processing area and storage capacity without increasing lateral dimensions, maintaining manufacturing compatibility while enabling higher data processing speeds through increased capacity and optimized data pathways.
Data Source
AI summary
A sensor device includes a first wafer structure and a second wafer structure bonded to the first wafer structure. The first wafer structure includes a first substrate, an integrated circuit layer integrated with the first substrate, and a three-dimensional (3D) NAND memory cell array integrated with the integrate circuit layer. The integrated circuit layer and the 3D NAND memory cell array are located at the same side of the first substrate. The second wafer structure includes a second substrate and a sensing module of a sensor integrated with the second substrate. A manufacturing method of the sensor device includes bonding the second wafer structure to the first wafer structure. A side of the first wafer structure where the 3D NAND memory cell array is located is bonded to a side of the second wafer structure where the sensing module is located.