3D NAND SGS Transistor Latent Defect Prevention
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Solution Overview
Problem
In three-dimensional (3D) memory structures, latent defects in source select side transistors (SGS transistors) can lead to electrical shorts, causing data loss due to malfunction during memory operations, as these defects may not be detectable during testing and worsen over time under normal operating voltages.
Innovation Solution
A stress voltage test is applied between the control gate and substrate of SGS transistors to detect threshold voltage deviations, enabling a sub-block mode where data is not written to memory cells in affected sub-blocks, thereby preventing data loss and preserving capacity by using only operational SGS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stress voltage test is applied to detect latent defects in SGS transistors, then data integrity is improved, but device complexity and manufacturing time increase
Solution Approach 1:
The patent applies a stress voltage test during the manufacturing process to detect latent defects in SGS transistors before they are deployed in normal operation. This preliminary detection action identifies defective transistors early, allowing the system to prevent future data loss without requiring complex runtime detection mechanisms.
Solution Approach 2:
The patent changes the voltage parameter by applying an elevated stress voltage (e.g., 20V) during testing, which is higher than normal operating voltages. This parameter change reveals latent defects that would not be detectable under normal conditions, improving reliability without requiring structural modifications to the device.
2Reliability
If defective sub-blocks are isolated to prevent data loss, then data integrity is improved, but storage capacity is reduced
Solution Approach 1:
The patent divides the memory structure into discrete sub-blocks that can be independently managed. When a latent defect is detected in a specific SGS transistor, only the affected sub-block is isolated and marked as ineligible for data storage, while the rest of the memory structure remains fully operational. This segmentation minimizes the impact on total storage capacity.
Solution Approach 2:
The patent discards (marks as ineligible) only the specific sub-blocks containing defective SGS transistors, while preserving and continuing to use all other operational sub-blocks. This selective discarding approach prevents data loss in affected areas while maximizing the utilization of healthy memory regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stress voltage test effectively identifies and mitigates latent defects in SGS transistors, ensuring data integrity by isolating defective sub-blocks and maintaining data storage capacity in operational sections of the memory structure.
Implementation Method 1
A stress voltage test is applied between the control gate and substrate of SGS transistors to detect threshold voltage deviations
Data Source
AI summary
Technology is disclosed for detecting latent defects in non-volatile storage systems. Prior to writing data, a stress voltage is applied to SGS transistors in a 3D memory structure. After applying the stress voltage, the Vt of the SGS transistors are tested to determine whether they meet a criterion. The criterion may be whether a Vt distribution of the SGS transistors falls within an allowed range. If the criterion is not met, then a sub-block mode may be enabled. In the sub-block mode, data is not written to memory cells in a sub-block that contains SGS transistors whose Vt does not meet the criterion. Hence, the possibility of data loss due to defective SGS transistors is avoided. However, in the sub-block mode, data is written to memory cells in a sub-block that does not contain SGS transistors whose Vt does not meet the criterion. Hence, data capacity is preserved.