Solid-State Devices TRIZ Cases

A semiconductor device method uses carbon-containing silicon oxide to form precise sidewalls on stacked gates.

An anisotropic diffusion film disperses light from organic light emitting diodes to improve side luminance.

Segmented hole transport layers with distinct HOMO gradients resolve the trade-off between driving voltage and device lifespan in OLEDs.

A programmable die address bus configures stacked integrated circuits to support flexible data bus widths.

A replacement buried source layer contacts vertical channel bottoms to form electrical connections.

Alternating dielectric layers with different refractive indices tune color appearance and protect device lifetime without compromising photon collection.

A stacked first and second electrode metal layer structure extends beyond the encapsulating structure edge to block external water vapor.

Apertures in the second electrode reduce stray capacitance, improving quantum efficiency without complex manufacturing.

A method forms an imprint layer with a contact hole overlapping a foundation conductive layer to enable direct electrical connection.

Metal semiconductor metal binary switch memory device minimizes leakage through unselected word lines, maximizing bit line output voltage.

A thin film transistor array substrate uses a supporting layer to define contact holes through insulating layers.

Varying hole dimensions in the substrate improve ESD robustness while reducing device complexity and leakage.

Acute memory gate corners concentrate electric fields to enhance charge injection efficiency in nonvolatile semiconductor devices.

Selective insulation removal creates uniform depth side contacts, reducing buried bit line resistance.

Multi-contact Hall sensors reduce residual offset error through Iu-biasing and Ui-forcing modes that maintain constant current or voltage across phases.

A thin film transistor uses a metal catalyst to crystallize amorphous silicon into polysilicon with controlled grain boundaries.

Differential etching rates preserve side wall films to resolve hole diameter non-uniformity and improve manufacturing yield.

Stacking a wavelength conversion layer between a porous layer and a reflective layer prevents light mixing in narrow pixel intervals.

Patterned organic light emitting layer arranges blue and yellow zones on a single plane to generate white illumination.

Shielding parts block mobile ions from passivation films to maintain non-volatile memory data storability.

Edge-trimming and sacrificial layer removal expose the active layer, increasing light transmission while maintaining electrical connectivity.

A semiconductor design merges driving transistors to share a common source drain region while maintaining independent individual source drains.

An array substrate embeds conductive structures within insulating layer apertures to maintain electrical connectivity.

Back-to-back DMOS transistors with voltage limiting components protect bus drivers from overvoltage damage while maintaining full output voltage swing.

An interfacial layer buffers tensile stress between conductive structures and flowable CVD insulation during semiconductor fabrication.

Nanostructured acceptor particles embed in a donor layer to increase interface area, reducing dead islands and improving efficiency.

An OLED pixel integrates a photo diode and capacitor to detect brightness and adjust driving current, compensating for non-uniform decay.

A dummy word line biased at an intermediate voltage shields unselected NAND strings during programming operations.

A floating NISO node prevents minority carrier injection into the substrate during negative undershoot events, protecting against junction breakdown.

A vertical memory device uses a composite ferroelectric and antiferroelectric layer to trap charge efficiently.

A composite protective layer using boron nitride and aluminum nitride enhances light extraction from the device.

Dual adhesive members bond a transparent window to a stepped structure, preventing moisture infiltration that reduces light extraction efficiency.

A photosensitive switching apparatus enables precise electrical contact testing on printed circuit boards using electromagnetic radiation.

Multi-layer reflection structures with varying refractive indices improve light extraction while preventing electrode separation in flip-chip LEDs.

High-aspect-ratio channels filter vaporized atoms to reduce feathering and enable high-resolution patterning for near-to-eye displays.

A touch panel design segments common electrode blocks with gaps and bridge electrodes to reduce parasitic capacitance between layers.

Periodic oxidizing agent supply during deposition resolves the contradiction between oxygen addition and film smoothness while removing chlorine residues.

Segmented via hole etching prevents coking residues and electrostatic discharge in IGZO-based array substrates.

A semiconductor antenna switch circuit uses segmented transistor groups to manage signal transmission across multiple frequency bands.

Insulating layer grooves guide hydrogen release from semiconductor layers during thermal treatment, preventing signal line damage.

A variable resistance memory system uses segmented arrays with distinct material doping to separate high-speed buffer operations from high-density storage.

Applying elevated stress voltages detects latent defects in 3D NAND SGS transistors, enabling sub-block isolation to preserve storage capacity.

A multi-layer stack structure positions common layers to cover sidewalls of the charge generation layer in an OLED display.

Routing a flexible printed circuit board through an opening in the display panel prevents separation caused by high-tension 180-degree bends.

Separating program and read paths in a memory cell protects the read transistor from continuous stress during operations, resolving endurance degradation.

An overlapping inner area structure improves adhesion and reduces dead spaces caused by boundary misalignment in display manufacturing.

Annealing organic passivation films releases trapped moisture, preventing film separation during subsequent baking processes.

Iterative temperature control of a high coefficient thermal expansion layer compensates for memory die warpage, improving three-dimensional bonding yield.

A self-aligned back side deep trench isolation structure shields pixel sensors from adjacent circuit interference.