Floating NISO Node for Double Isolation Transistors
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Solution Overview
Problem
Double lateral junction isolated DEMOS and LDMOS transistors used in high side gate drivers for motor drive applications experience negative undershoot of the NISO node during dynamic operation, leading to minority carrier injection into the substrate, which can result in malfunction and damage due to conventional connection methods.
Innovation Solution
Implementing a floating NISO node for the low side LDMOS or DEMOS transistor in high side gate drivers, where the NISO node is not connected to a bond pad, providing full isolation of the source and drain from ground and boot node, thereby preventing minority carrier injection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the NISO node is connected to a bond pad in conventional double lateral junction isolated transistors, then the device structure is complete and manufacturable, but negative undershoot during dynamic operation causes minority carrier injection into the substrate leading to malfunction and damage
Solution Approach 1:
The patent extracts the NISO node connection from the conventional bond pad connection, making the NISO node floating instead of connected. This extraction eliminates the harmful minority carrier injection path while maintaining the structural integrity of the device through alternative isolation mechanisms.
Solution Approach 2:
Instead of connecting the NISO node to a bond pad as in conventional design, the patent inverts the approach by leaving it floating and unconnected. This inversion of the conventional connection principle resolves the negative undershoot issue while maintaining device functionality.
2Reliability
If conventional connection methods are used for the NISO node, then the transistor can be manufactured with standard processes, but voltage rating is limited due to junction breakdown at high voltages
Solution Approach 1:
The patent extracts the NISO node from the conventional connection to ground or bond pad, creating a floating node that can sustain higher voltages without junction breakdown. This extraction allows the transistor to achieve higher voltage ratings while using standard manufacturing processes.
3Reliability
If double lateral junction isolation is implemented with conventional NISO connection, then voltage rating is improved by several volts, but minority carrier injection occurs during switching causing device malfunction
Solution Approach 1:
The patent extracts the harmful connection path by making the NISO node floating, which removes the pathway for minority carrier injection into the substrate while preserving the voltage rating benefits of double lateral junction isolation.
Solution Approach 2:
The patent converts the potentially harmful floating node into a beneficial feature by demonstrating that the floating NISO node configuration actually protects against minority carrier injection while maintaining high voltage rating, turning a conventional weakness into a strength.
Data Source
AI summary
A semiconductor device includes at least a first transistor including at least a second level metal layer (second metal layer) above a first level metal layer coupled by a source contact to a source region doped with a first dopant type. The second level metal layer is coupled by a drain contact to a drain region doped with the first dopant type. A gate stack is between the source region and drain region having the second level metal layer coupled by a contact thereto. The second level metal layer is coupled by a contact to a first isolation region doped with the second dopant type. The source region and drain region are within the first isolation region. A second isolation region doped with the first dopant type encloses the first isolation region, and is not coupled to the second level metal layer so that it electrically floats.