Interfacial Layer Reduces Tensile Stress in Flowable CVD Insulation
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Solution Overview
Problem
The challenge in semiconductor device fabrication lies in reducing tensile stress at the interface between conductive structures and insulation layers, which can lead to electrical bridging and void formation, especially in highly integrated devices with fine pitch sizes.
Innovation Solution
A method involving the formation of an interfacial layer using atomic layer deposition (ALD) with trisilylamine and oxygen gas, followed by a flowable chemical vapor deposition (CVD) process to create a cured and annealed insulation layer, reducing tensile stress and preventing electrical bridging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a flowable CVD process is used to form the first insulation layer, then the insulation layer can be formed conformally and fill gaps effectively, but tensile stress is generated at the interface with conductive structures leading to void formation and electrical bridging
Solution Approach 1:
An interfacial layer is introduced between the conductive structures and the first insulation layer. This interfacial layer acts as a stress buffer that reduces the tensile stress generated during the flowable CVD process, preventing void formation and electrical bridging while maintaining conformal coverage and effective gap filling.
Solution Approach 2:
The stress characteristics of the interface are modified by introducing a material layer with different mechanical properties. The interfacial layer changes the stress distribution parameters, reducing tensile stress concentration at the interface between the conductive structures and the insulation layer, thereby preventing reliability issues.
2Productivity
If integration density is increased with fine pitch sizes, then device functionality is enhanced, but photolithography limitations and stress management become more difficult
Solution Approach 1:
The insulation layer formation process is segmented into multiple functional layers: an interfacial layer for stress management and a first insulation layer for electrical isolation. This segmentation allows each layer to be optimized for its specific function, enabling high integration density while managing the increased complexity of stress control in fine pitch devices.
Solution Approach 2:
The interfacial layer serves as an intermediary between the conductive structures and the insulation layer, specifically addressing the stress management challenges that arise with increased integration density and fine pitch sizes. This mediator layer simplifies the overall process by decoupling the stress management function from the insulation function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and integration density of semiconductor devices by minimizing stress and voids, ensuring high productivity and reliability without degrading device performance.
Implementation Method 1
the interfacial layer reduces a tensile stress generated at an interface between the conductive structures and the first insulation layer while the first insulation layer is formed
Implementation Method 2
curing the flowable insulation layer to form a cured insulation layer
Implementation Method 3
annealing the cured insulation layer
Implementation Method 4
conformally forming an interfacial layer on the substrate in contact with the conductive structures; conformally forming the interfacial layer comprises forming using an atomic layer deposition (ALD) process
Data Source
AI summary
In a method of fabricating a semiconductor device, isolation structures are formed in a substrate to define active regions. Conductive structures are formed on the substrate to cross over at least two of the active regions and the isolation structures, the conductive structures extending in a first direction. An interfacial layer is conformally formed on the substrate in contact with the conductive structures. A first insulation layer is provided on the interfacial layer, wherein the first insulation layer is formed using a flowable chemical vapor deposition (CVD) process, and wherein the interfacial layer reduces a tensile stress generated at an interface between the conductive structures and the first insulation layer while the first insulation layer is formed.