Array Substrate Via Hole Etching Residue Prevention
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Solution Overview
Problem
In the manufacturing of array substrates for TFT-LCDs, the use of IGZO active layers with SiOx or SiOx/SiNx gate insulating materials leads to long etching times and residual via hole residues, causing contact resistance issues and electrostatic discharge during screen splicing, which can result in display abnormalities and reduced yield.
Innovation Solution
A manufacturing method involving the deposition of metal layers, gate insulating layers, and passivation layers with strategically formed via holes, where the first via hole reaches the surface of the first metal layer in the in-plane region and the second via hole reaches the surface of the second metal layer, with the transparent conductive layer filling these holes, and additional via holes in the out-of-plane region to avoid deep and shallow hole formation, reducing static electricity accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single drilling process is used to form deep holes and shallow holes, then the process is simple, but via hole coking residue occurs and contact resistance increases
Solution Approach 1:
The patent divides the drilling process into two separate operations: a first drilling process that forms deep holes through the gate insulating layer, and a second drilling process that forms shallow holes through the passivation layer. This segmentation allows each drilling process to be optimized independently, preventing coking residue by ensuring that shallow holes are drilled after the deep holes are completed, thereby maintaining low contact resistance while keeping the overall manufacturing approach feasible.
Solution Approach 2:
The patent performs the deep hole drilling as a preliminary action before drilling the shallow holes. By completing the deep hole etching first, the process ensures that subsequent shallow hole drilling does not cause coking residue, as the etching conditions are already established and optimized from the first drilling process.
2Manufacturing precision
If trenching of the gate insulating layer is added to solve via hole residue, then via hole residue is eliminated, but static electricity accumulates and electrostatic discharge occurs during screen splicing
Solution Approach 1:
The patent applies different drilling strategies to different regions of the substrate. In the display area (in-plane region), it uses the segmented drilling process with offset via holes to eliminate residue. In the non-display area (out-of-plane region), it uses a combined drilling approach to avoid static electricity accumulation. This local differentiation resolves the contradiction by applying the appropriate solution to each specific region's requirements.
Solution Approach 2:
Instead of uniformly applying the trenching method across the entire substrate to eliminate via hole residue, the patent inverts the approach by using region-specific drilling strategies. The inversion lies in recognizing that the solution suitable for the display area (trenching/segmented drilling) may be harmful in the non-display area (causing static electricity), so the methodology is reversed or adapted for different regions.
3Manufacturing precision
If gate insulating layer drilling is performed in both upper and lower half screens, then via hole residue is prevented, but static electricity accumulates during drying process
Solution Approach 1:
The patent implements region-specific drilling processes: the display area uses segmented drilling with offset via holes to prevent residue, while the non-display area uses combined drilling to prevent static electricity accumulation. This local quality differentiation ensures that each region's specific requirements are met without compromising overall panel reliability.
Solution Approach 2:
The patent converts the potential harm of static electricity accumulation into a benefit by strategically placing via holes and using offset positioning in the display area, while in the non-display area, it accepts the combined drilling approach. The 'harm' of potentially longer etching times is converted into the benefit of preventing static electricity and ensuring panel reliability through careful process design and region differentiation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for controlled etching times, reduces coking residues, ensures normal contact resistance, and prevents electrostatic discharge, thereby improving display performance and yield while reducing production costs.
Implementation Method 1
depositing a first metal layer on an in-plane region and an out-of-plane region of the substrate
Implementation Method 2
depositing a gate insulating layer on the substrate and the first metal layer
Implementation Method 3
forming a first via hole in the in-plane region of the gate insulating layer
Data Source
AI summary
Disclosed is a manufacturing method of an array substrate, comprising steps of: depositing a first metal layer on a substrate; depositing a gate insulating layer on the substrate and the first metal layer, and forming a first via hole in the in-plane region of the gate insulating layer; depositing a second metal layer in an in-plane region and an out-of-plane of the gate insulating layer, wherein the second metal layer located in the in-plane region fills the first via hole; depositing a passivation layer on the second metal layer and the gate insulating layer, and forming a second via hole in the in-plane region of the passivation layer; forming a third via hole and a fourth via hole in the out-of plane region of the passivation layer, respectively; depositing a transparent conductive layer in the in-plane region and in the out-of-plane region of the passivation layer, respectively.