Replacement Buried Source Line in 3D Memory
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently forming electrical connections between vertical semiconductor channels and a common source region, particularly in providing inexpensive and efficient methods for these connections using a replacement buried source layer.
Innovation Solution
The implementation of a method to form semiconductor pillar structures with a source-level semiconductor material layer that contacts the bottom end portions of vertical semiconductor channels and laterally surrounds them, within a cavity formed by removing a sacrificial layer, allowing for efficient electrical connections through an alternating stack of insulating and conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a replacement buried source layer is used to form electrical connections between vertical semiconductor channels and a common source region, then manufacturing cost is reduced and efficiency is improved, but the process complexity increases due to the need to form and remove sacrificial layers
Solution Approach 1:
A sacrificial layer is formed at the source level before forming the alternating stack of insulating and conductive layers. This preliminary action creates a cavity that will later be filled with semiconductor material to form the replacement buried source layer, enabling cost-effective electrical connections while managing process complexity through structured sequencing
Solution Approach 2:
The sacrificial layer acts as an intermediary element that is temporarily introduced to enable the formation of the replacement buried source layer. After the alternating stack is formed around the sacrificial layer, the sacrificial layer is removed and the cavity is filled with semiconductor material, using the intermediary to achieve the final electrical connection structure
2Device complexity
If vertical semiconductor channels are directly connected to a common source region, then device structure is simplified, but electrical connection efficiency and performance are reduced
Solution Approach 1:
The replacement buried source layer extends laterally around the semiconductor pillar structures in addition to contacting the bottom ends of vertical channels. This three-dimensional configuration provides multiple electrical connection pathways simultaneously, improving connection efficiency while maintaining a integrated structure that doesn't significantly increase device complexity
3Reliability
If a replacement buried source layer is formed by removing sacrificial material and filling with semiconductor material, then electrical connections are improved, but manufacturing steps are increased
Solution Approach 1:
The formation of the replacement buried source layer is merged with the formation of the alternating stack. The sacrificial layer is formed first, then the alternating stack of insulating and conductive layers is formed around it in a combined process sequence. Afterward, the sacrificial layer removal and semiconductor material filling are performed as integrated steps to form the final electrical connection structure
Data Source
AI summary
An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures. The source-level semiconductor material layer may be electrically isolated from a substrate semiconductor material layer in the substrate by a series connection of two p-n junctions having opposite polarities.