Vertical Memory Device with Ferroelectric-Antiferroelectric Composite

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Solution Overview

Problem

Conventional non-volatile memory devices require higher operating voltages and have slower writing/erasing speeds, leading to poor operating endurance.

Innovation Solution

A storage memory device with a vertical field effect transistor structure, incorporating a doped hafnium oxide-based ferroelectric layer and a zirconium oxide-based antiferroelectric layer, which reduces operating voltage and enhances writing/erasing speed through negative capacitance and improved charge trapping properties.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If high-k oxide is used in the insulating barrier to reduce operating voltage, then the operating voltage is reduced, but the writing/erasing speed becomes slower and operating endurance deteriorates

Engineering Contradiction:
Improveoperating voltageVSAvoidwriting/erasing speed
Core Design Contradiction:
Use of energy by moving objectVSSpeed

Solution Approach 1:

The patent employs a composite structure consisting of a ferroelectric layer (HfO2-based) and an antiferroelectric layer (ZrO2-based) stacked together. This composite material approach allows the device to achieve both low operating voltage (through the ferroelectric layer's negative capacitance) and fast writing/erasing speed (through the antiferroelectric layer's rapid polarization switching), thereby resolving the contradiction between voltage reduction and speed maintenance.

Inventive Principle:
Principle #40Composite materials

2Use of energy by moving object

If high-k oxide is used in the insulating barrier, then operating voltage is reduced, but operating endurance becomes poor

Engineering Contradiction:
Improveoperating voltageVSAvoidoperating endurance
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The combination of ferroelectric and antiferroelectric layers creates a composite structure where the antiferroelectric layer provides robustness and stability, improving operating endurance. The ferroelectric layer maintains low operating voltage through negative capacitance, while the antiferroelectric layer's fast switching capability ensures reliable write/erase operations, thus resolving the contradiction between voltage reduction and endurance improvement.

Inventive Principle:
Principle #40Composite materials

3Ease of manufacture

If conventional flash memory structure is used, then manufacturing is simpler, but leakage current is higher and operating speed is slower

Engineering Contradiction:
Improvestructure simplicityVSAvoidleakage current
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The patent changes the material parameters by introducing a ferroelectric layer with negative capacitance properties and an antiferroelectric layer with fast switching characteristics. This parameter change enables the device to achieve lower leakage current (through improved charge trapping efficiency) and faster operating speed (through rapid polarization switching), while maintaining a vertical transistor structure that is relatively easy to manufacture using existing semiconductor fabrication processes.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The device achieves significantly lower operating voltage and faster operating speed, with writing/erasing speeds up to 50 ns, improving endurance and reducing power consumption and leakage current.

Implementation Method 1

The ferroelectric layer is made of a doped hafnium oxide-based material that has a predominantly orthorhombic phase and that exhibits a negative capacitance

Methodology Applied
Scientific EffectNegative capacitance:

Implementation Method 2

a charge trapping layer formed on the insulating layer

Methodology Applied
Scientific EffectCharge trapping:

Data Source

PatentUS20210005733A1Storage memory device
Publication Date: 2021.01.07 NATIONAL TAIWAN NORMAL UNIVERSITY
  • US20210005733A1 patent drawing
  • US20210005733A1 patent drawing
  • US20210005733A1 patent drawing

AI summary

A storage memory device includes a vertical field effect transistor including a semiconductor substrate; a pillar extending upwardly from the substrate and containing a source, a drain, and a channel disposed therebetween; a first insulating layer surrounding the channel; a stacked structure surrounding the first insulating layer; and a gate unit. The stacked structure includes a charge trapping layer and a composite element. The composite element includes a ferroelectric layer made of a doped hafnium oxide-based material that has a predominantly orthorhombic phase and exhibits a negative capacitance; and an antiferroelectric layer made of a zirconium oxide-based material that has a predominantly tetragonal phase.