Semiconductor Device Sidewall Formation via Selective Etching

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The existing gate etching process in semiconductor manufacturing faces challenges due to uneven silicon oxide mask layer thicknesses above stacked gates, which reduces the process window and requires a new vapor phase wet etching process, increasing manufacturing costs and risking damage to interlayer dielectric layers.

Innovation Solution

A method involving the deposition of a carbon-containing silicon oxide thin layer, followed by a non-carbon-containing silicon oxide layer, planarization using chemical mechanical polishing, and selective wet etching to remove the non-carbon-containing silicon oxide layer, while retaining the carbon-containing silicon oxide as sidewalls, thereby maintaining the integrity of the interlayer dielectric layer and reducing manufacturing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a new vapor phase wet etching process is introduced to remove the silicon oxide mask layer, then the thickness non-uniformity is eliminated, but the manufacturing cost increases and the interlayer dielectric layer may be damaged

Engineering Contradiction:

Improvethickness uniformity of silicon oxide mask layerVSAvoidmanufacturing cost and process complexity

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

A protective film layer is deposited on the interlayer dielectric layer before the wet etching process. This protective layer prevents the etching solution from damaging the interlayer dielectric layer during the removal of the silicon oxide mask layer, thereby eliminating the need for new vapor phase wet etching equipment and reducing manufacturing costs

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The protective film layer acts as an intermediary between the wet etching solution and the interlayer dielectric layer. It allows the etching process to proceed while protecting the underlying dielectric layer from damage, solving the contradiction between achieving uniform thickness removal and avoiding equipment investment

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If the silicon oxide mask layer is not completely removed, then the process window is reduced, but the gate structure integrity may be compromised

Engineering Contradiction:

Improveprocess window for subsequent etchingVSAvoidgate structure integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The wet etching process with protective film enables selective removal of the silicon oxide mask layer while preserving the gate structure. The protective film ensures that etching occurs only where intended, maintaining gate integrity while achieving complete mask layer removal for optimal process window in subsequent interlayer dielectric etching and gate cut-off processes

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the removal of uneven silicon oxide mask layers without new equipment, protecting the interlayer dielectric layer and enhancing the semiconductor device's performance by reducing crosstalk between gates, while maintaining compatibility with existing processes.

Implementation Method 1

planarization using chemical mechanical polishing

Methodology Applied

Scientific EffectChemical mechanical polishing:

Implementation Method 2

selective wet etching to remove the non-carbon-containing silicon oxide layer

Methodology Applied

Scientific EffectSelective wet etching:

Implementation Method 3

deposition of a carbon-containing silicon oxide thin layer

Methodology Applied

Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Data Source

PatentUS11600493B2Semiconductor device and method for manufacturing the same

Publication Date: 2023.03.07 SHANGHAI HUALI MICROELECTRONICS CORP

AI summary

The present disclosure provides a method for manufacturing a semiconductor device, including: providing a substrate having a plurality of stacked gates with silicon nitride mask layer and silicon oxide mask layer formed on top of the surface; depositing a first carbon-containing silicon oxide thin layer; depositing a second non-carbon-containing silicon oxide layer to fill the gaps between adjacent stacked gates; and planarizing the first silicon oxide thin layer and the second silicon oxide layer by applying the silicon nitride mask layer as a stop layer, removing the second silicon oxide layer, and forming the first sidewalls with the first silicon oxide thin layer on the sides of the stacked gates. The present disclosure further provides a semiconductor device made with the method thereof. The present disclosure can remove the silicon oxide mask layer above the stacked gates through a simple process flow.