Memory Cell Program Read Path Separation for Endurance
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Solution Overview
Problem
Conventional non-volatile memory cells experience severe transconductance degradation and erase current degradation due to high endurance counts, leading to reduced operation performance over time, as they use a common path for both program and read operations, causing continuous stress on the read transistor.
Innovation Solution
A memory cell design with distinct program and read paths, utilizing a coupling device, read transistor, selection transistors, erase device, program transistor, and program selection transistor, which allows the read transistor to avoid continuous stress during program and erase operations by using different transistors for each operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common path is used for both program and read operations in conventional non-volatile memory, then device complexity is reduced, but transconductance degradation and erase current degradation occur due to continuous stress on the read transistor during program operations
Solution Approach 1:
The memory cell is divided into separate program path and read path components. The program transistor and read transistor are distinct, allowing independent optimization of each path. This segmentation eliminates the stress accumulation on the read transistor during program operations, directly resolving the technical contradiction between reliability and device complexity.
Solution Approach 2:
The read transistor is extracted from the program path, creating a dedicated read path that is independent of program operations. This extraction prevents the read transistor from experiencing continuous stress during programming, thereby improving endurance without significantly increasing overall device complexity.
2Duration of action of moving object
If high endurance count is achieved through repeated program and erase operations, then memory capacity utilization increases, but transconductance degradation leads to erase current degradation and reduced sensor margin
Solution Approach 1:
By segmenting the memory cell into separate program and read paths with dedicated transistors, the read transistor is protected from degradation during program operations. This allows high endurance counts to be achieved without the transconductance degradation that previously compromised operation performance and sensor margin.
Solution Approach 2:
The design provides beforehand cushioning by creating a protected read path that is isolated from program operation stress. This protective structure ensures that even after repeated program and erase operations, the read transistor maintains its performance characteristics, preserving sensor margin and operation reliability throughout the memory's lifespan.
Data Source
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AI summary
A memory cell (100) includes a coupling device (CD), a read transistor (RT), a first read selection transistor (RST1), a second read selection transistor (RST2), an erase device (ED), a program transistor (PT), and a program selection transistor (PST) . The coupling device (CD) is formed on a first doped region (Reg1). The erase device (ED) is formed on a second doped region (Reg2). The read transistor (RT), the first read selection transistor (RST1), the second read selection transistor (RST2), the program transistor (PT), and the program selection transistor (PST) are formed on a third doped region (Reg3). A gate terminal of the coupling device (CD) is coupled to a common floating gate. A gate terminal of the erase device (ED) is coupled to the floating gate. During a program operation, electrical charges are moved to the common floating gate. During an erase operation, electrical charges are ejected from the common floating gate to the erase device (ED).