Side Contact Formation in Semiconductor Devices
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Solution Overview
Problem
Conventional semiconductor devices with vertical channels face challenges in forming side contacts due to the shrinking dimensions, which makes it difficult to selectively expose and uniformly form side contacts on the active region sidewalls, limiting the reduction of buried bit line resistance and affecting device performance.
Innovation Solution
A method is developed to form side contacts by etching semiconductor substrates with a hard mask pattern, creating recesses and using etch stop and sacrificial layers to achieve uniform depth and selective exposure of sidewalls, enabling the formation of Ohmic-like contacts between the active region and buried bit line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the width of the active region is decreased and the depth becomes deeper to achieve higher integration, then the device integration is improved, but it becomes difficult to form a side contact that selectively exposes any one sidewall of the active region at a uniform depth
Solution Approach 1:
The patent divides the sidewall protection into segments by forming insulation layers on both sidewalls and then selectively removing portions. The etch stop layer is positioned at different depths to create segmented exposure zones, allowing precise control over which sidewall is exposed and at what depth, thereby solving the uniformity problem in highly integrated devices with narrow, deep active regions.
Solution Approach 2:
The patent performs preliminary actions by forming the insulation layers and etch stop layers before the side contact formation process. The etch stop layer is pre-positioned at the desired depth to control the exposure uniformity in advance, enabling subsequent side contact formation to proceed with consistent depth across all active regions even as device dimensions shrink.
2Ease of manufacture
If ion implantation is used to form the buried bit line, then the formation process is simple, but the resistance of the buried bit line cannot be sufficiently decreased in shrunken semiconductor devices
Solution Approach 1:
The patent merges the buried bit line formation with side contact formation processes. By creating recesses that expose the sidewalls and forming side contacts simultaneously, the method achieves both low resistance through metal filling and proper electrical coupling, overcoming the limitation of ion implantation alone in highly scaled devices.
3Reliability
If a side contact is formed to couple the active region and buried bit line, then the electrical coupling is improved, but the formation becomes increasingly difficult as device dimensions shrink
Solution Approach 1:
The patent introduces an etch stop layer as an intermediary element that mediates between the insulation layer and the active region. This intermediary controls the etching depth and ensures uniform exposure of the sidewall at the correct position, simplifying the overall side contact formation process while maintaining reliable electrical coupling in shrunken devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the formation of side contacts at a uniform depth and desired position, reducing the resistance of the buried bit line and improving semiconductor device performance by enabling effective coupling between the active region and buried bit line.
Implementation Method 1
forming an etch stop layer filling a portion of each gap between the active regions
Implementation Method 2
forming a recess exposing the insulation layer formed on any one sidewall from among the first sidewall and the second sidewall
Data Source
AI summary
A method for fabricating a semiconductor device includes forming a plurality of active regions, each having a first sidewall and a second sidewall, by etching a semiconductor substrate, forming an insulation layer on the first sidewall and the second sidewall, forming an etch stop layer filling a portion of each gap between the active regions, forming a recess exposing the insulation layer formed on any one sidewall from among the first sidewall and the second sidewall, and forming a side contact exposing a portion of any one sidewall from among the first sidewall and the second sidewall by selectively removing a portion of the insulation layer.