3D NAND Memory Source Line Segmentation for Threshold Voltage Control
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Solution Overview
Problem
The reliability of 3-dimensional semiconductor devices is compromised due to varying threshold voltages of memory cells adjacent to the drain selection transistor, affecting program, read, and erase operations, primarily because of resistance issues related to the source line.
Innovation Solution
The semiconductor device employs a method where cell strings are operated by categorizing memory cells into groups, with program and read operations performed sequentially from either the source lines or bit lines, and erase operations are managed using incremental step pulse erase techniques to control voltages applied to bit lines, source lines, and word lines, thereby reducing resistance and maintaining data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3-dimensional semiconductor device with vertically formed cell strings is used to overcome integration limits, then degree of integration is improved, but threshold voltage variation of memory cells adjacent to drain selection transistor increases due to source line resistance
Solution Approach 1:
The patent segments the cell strings into two groups: first cell strings connected to first source lines, and second cell strings connected to second source lines. This segmentation allows independent voltage control for each group, enabling compensation for source line resistance effects on threshold voltage variation without compromising the high integration benefits of the 3D structure.
Solution Approach 2:
The patent applies different voltage conditions to different regions of the device. By providing different voltages to the first and second source lines based on the operational state (program, read, or erase), the system locally compensates for resistance effects in specific regions, thereby controlling threshold voltage variation while maintaining the integrated 3D architecture.
2Reliability
If sequential program operation from memory cells adjacent to source lines is performed, then program operation reliability is improved, but operation time increases
Solution Approach 1:
The patent divides the program operation into two independent sequential processes: one for first memory cells in first cell strings, and another for second memory cells in second cell strings. By segmenting the operation and executing them concurrently or in optimized sequence, the system improves program reliability through controlled voltage application while minimizing total operation time.
Solution Approach 2:
The patent employs periodic incremental step pulse erase operations with verification steps. This periodic approach allows the system to perform multiple programming cycles with intermediate verification, improving reliability by ensuring proper programming while managing total operation time through efficient periodic execution rather than continuous operation.
3Reliability
If incremental step pulse erase technique is used to control voltages, then threshold voltage distribution width increase is inhibited, but erase operation complexity increases
Solution Approach 1:
The patent applies incremental step pulse erase technique separately to first and second cell strings by controlling voltages on first and second source lines independently. This segmentation allows the complex erase operation to be broken into manageable steps for each group, inhibiting threshold voltage distribution width increase while making the overall complex process more controllable and systematic.
Solution Approach 2:
The patent applies different voltage conditions to different regions during erase operations. By providing specific voltages to first and second source lines based on the operational state, the system locally controls the erase process to inhibit threshold voltage distribution width increase in each region, managing the complexity through localized voltage control rather than uniform treatment.
4Reliability
If separate source lines for different cell string groups are provided, then threshold voltage control is improved, but device structure complexity increases
Solution Approach 1:
The patent segments the source line structure into first source lines connected to first cell strings and second source lines connected to second cell strings. This segmentation enables independent voltage control for improved threshold voltage management while organizing the complex structure into manageable, repeating units that can be systematically implemented in the 3D vertical architecture.
Data Source
AI summary
A semiconductor device and a method of operating the same. The semiconductor device may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of cell strings extending substantially perpendicular to a semiconductor substrate, the plurality of cell strings sharing a plurality of bit lines, and a plurality of source lines respectively connected to the cell strings and word lines. Page buffers, connected to the bit lines, may store data. A selection switch portion may selectively transmit a voltage corresponding to data stored in the page buffers, and voltages supplied from an external source, to the bit lines and the source lines during the program operation, the read operation and the erase operation. A control circuit may control the page buffers and the selection switch portion.