Read-Only Memories TRIZ Cases

Programming drain-side select gate transistors to a stable threshold voltage minimizes cumulative read disturb caused by charge migration.

A cross-coupled high-voltage latch with low-voltage n-channel MOS transistors selectively grounds inverter outputs to ensure reliable data transfer.

A memory sector derives distinct reference currents for odd and even word lines to improve logic state determination accuracy.

A data storage device controller reads target memory cells using read biases and obtains discrimination data to identify unreliable bits within data chunks.

A flash memory controller detects optimal read voltages by counting cells in adjacent threshold voltage ranges to minimize read errors.

Selective program voltage adjustment preserves high-speed operation in reliable memory regions while applying conservative settings to degraded areas.

A memory controller uses segmented read processors to detect optimal voltages and skip unnecessary retry operations.

A semiconductor device stacks memory and arithmetic circuits in overlapping regions to suppress area increase.

A memory device adapts inhibit voltages based on programming loop counts to suppress leakage currents in unselected cells.

A memory controller adjusts sense voltage using stored training sequences to ensure accurate data retrieval.

A control circuit temporarily raises bit line voltage to a light erase level before write verify operations.

A semiconductor memory device uses a dummy count clock to pre-output data before normal operation.

Dynamic bitline bias adjustment during programming loops resolves threshold voltage shift and read noise issues while maintaining fast speed.

A memory access controller circuit determines data use frequency to select encoding levels for multi-bit flash memory cells.

A memory system updates maximum program loop counts to identify defective blocks during stage-wise programming operations.

A SONOS transistor uses Fowler-Nordheim tunneling at the source or drain to store electrons, enabling dual switch and memory functions.

A sensing circuit adjusts precharge current dynamically to maintain accurate data retention in nonvolatile memory devices.

Dynamic gate voltage and verify level adjustments mitigate threshold voltage shifts from temperature and cycles, reducing raw bit error rates.

A semiconductor memory device architecture couples normal and system blocks to enhance integration density.

Circuitry maps addresses to redundancy cells when primary write verification fails, resolving resistance drift errors without complex ECC decoding.

A non-volatile memory device uses a monitoring cell to dynamically adjust read voltage levels for accurate data retrieval.

A non-volatile memory programming method shifts pass voltage levels to lower states during verify operations.

Cross-coupled transistor latches maintain operational stability against internal voltage fluctuations, reducing current consumption and page buffer size.

A wordline driver circuit selectively powers individual drivers based on access requests to reduce active and standby energy consumption.

Segmented variable voltage precharging reduces bit line precharge time and improves data read speed in nonvolatile memory.

A memory architecture uses independently controlled voltage pumps to apply positive and negative biases for charge trapping.

Read recovery control circuitry recovers uncorrectable errors through adaptive stages, improving reliability without excessive complexity.

Sharing program bit lines across neighboring eFuse cells reduces resistivity to a quarter, enabling higher programming currents without expanding array area.

A controller adjusts data bit ratios in flash memory pages to alter threshold voltage distributions.

A semiconductor device diagnoses correction memory using distinct reading conditions to detect potential data errors.

Control logic segments planes into passed and failed groups, applying voltages only to failed planes to prevent threshold shifts.

A power circuit regulates operating voltage for flash memory controllers using a dedicated discharging unit.

A voltage generating circuit adjusts read levels via feedback to match memory cell threshold shifts.

A nonvolatile memory control circuit performs a post-program verify read to detect subtle word line resistance errors before status output.

Ramping word line voltages during program-verify operations to manage electrical stress in three-tier non-volatile memory arrays.

Embedded boundary scan cells verify flash memory connectivity to reduce testing time while maintaining comprehensive coverage.

A demapper circuit converts differential currents from storage transistors into probabilistic outputs using S-shaped mapping functions.

Negative voltage on word lines suppresses current leakage from over-erased cells, ensuring accurate read and program operations.

Multi-pass programming reduces verify operations in non-volatile storage, cutting programming time while maintaining data capacity.

Segmenting source lines in 3D NAND memory compensates for resistance-induced threshold voltage variation during program and erase operations.

A charge trap flash programming method injects tertiary electrons into the storage medium layer using controlled electric fields.

An RFID integrated circuit applies bias voltages to memory cells to determine data margin levels.

A non-volatile memory control unit verifies cell initial states via threshold voltage sensing.

Encoding repair data as fuse bit positions eliminates external storage, reducing test time and power consumption during memory defect management.

Storing interrupted pulse numbers allows precise resumption of NAND flash programming, avoiding unnecessary pulses and program disturb.

Computing confidence levels via log-likelihood ratios from hard reads improves memory throughput by avoiding time-consuming soft read operations.

A reversible polarity decoder architecture splits reverse bias voltage across word line and bit line decoders to enable smaller memory cell pitches.

Asymmetric insulating spacers in a vertical memory cell string reduce total thickness, enabling higher stacking density for neuromorphic computing.

Relocating negative level shifters to a peripheral region preserves memory core integrity by removing voltage conversion operations from the sensitive area.