Nonvolatile Memory Bit Line Precharge Optimization

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Nonvolatile memory devices face long bit line precharge times during data read operations, which significantly prolong the overall data read process.

Innovation Solution

The method involves using a variable voltage to precharge a bit line for a shorter initial period, followed by a precharge to a second voltage level using a sense node, allowing for quicker bit line evaluation and sensing, while disconnecting the sense node during this period to reduce overall precharge time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a bit line is precharged using the sense node of a page buffer, then the bit line reaches the desired voltage level, but the precharge time becomes excessively long

Engineering Contradiction:
Improvebit line voltage stabilityVSAvoidbit line precharge time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The precharge operation is divided into two distinct phases: a first precharge phase using a first voltage level to quickly establish initial voltage on the bit line, and a second precharge phase using a second voltage level to complete the voltage adjustment. This segmentation allows each phase to be optimized independently, reducing total precharge time while maintaining voltage stability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent dynamically adjusts the voltage level supplied to the bit line based on the precharge progress. The voltage level changes from the first voltage level to the second voltage level at a determined timing point, creating a dynamic precharge process that adapts to the actual voltage state of the bit line, thereby optimizing both speed and stability.

Inventive Principle:
Principle #15Dynamics

2Reliability

If the sense node is connected to the bit line during precharge, then voltage transfer occurs, but the precharge time is prolonged

Engineering Contradiction:
Improvevoltage transfer accuracyVSAvoidprecharge time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The sense node is precharged to the first voltage level before being connected to the bit line. This preliminary action ensures that when the connection is made, the voltage transfer occurs efficiently without requiring extended connection time, thus maintaining voltage transfer accuracy while minimizing the time the sense node remains connected to the bit line.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The connection between the sense node and bit line is made periodic rather than continuous. The sense node is connected to the bit line only during specific time intervals when voltage transfer is needed, and disconnected otherwise. This periodic connection reduces the overall time the sense node remains engaged with the bit line while ensuring proper voltage transfer occurs during active periods.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS8154948B2Method of operating nonvolatile memory device
Publication Date: 2012.04.10 SK HYNIX INC
  • US8154948B2 patent drawing
  • US8154948B2 patent drawing
  • US8154948B2 patent drawing

AI summary

A method of operating a nonvolatile memory device includes supplying a variable voltage of a first voltage level to a selected page buffer and supplying the variable voltage to a first bit line, coupled to a selected memory cell selected for data reading, for a first time period, cutting off the supply of the variable voltage to the first bit line, after the first time period, and precharging the first bit line to a second voltage level through a sense node of the selected page buffer, which is in a precharge state, evaluating a voltage of the first bit line, after the precharging of the first bit line, so that the voltage of the first bit line is shifted according to a program state of the selected memory cell, and sensing the voltage of the evaluated first bit line and latching data in the selected memory cell.