Read Recovery Control Circuitry for Memory Error Correction
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Solution Overview
Problem
Conventional memory sub-systems face challenges in reliably correcting and detecting errors, especially as the number of erroneous bits increases, leading to reduced data throughput and operational reliability due to process variability and smaller memory cells.
Innovation Solution
Incorporation of read recovery control circuitry that performs additional error detection and correction techniques beyond initial error correction operations, utilizing programmable recovery stages and adaptive error correction based on memory sub-system characteristics to enhance data reliability and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional error detection and correction techniques are implemented, then data reliability is improved, but device complexity increases
Solution Approach 1:
The error correction process is divided into multiple distinct stages: initial error correction using first error correction code, read recovery operations using second error correction code, and fallback to raw read operations. Each stage handles specific types of errors independently, improving reliability without requiring a single complex error correction system.
Solution Approach 2:
The system dynamically selects which error correction technique to apply based on the detected error type and severity. The read recovery control circuitry determines whether to perform initial error correction, read recovery, or raw read operations, adapting the error handling approach to match the actual data conditions rather than using a fixed complex system.
2Reliability
If multiple error correction stages are performed, then operational reliability is improved, but processing time increases
Solution Approach 1:
The system performs error correction stages selectively rather than always executing all stages. The read recovery control circuitry determines whether initial error correction is sufficient or if read recovery operations are needed, avoiding unnecessary processing time while maintaining reliability when errors are present.
Solution Approach 2:
Initial error correction is performed first as a preliminary step before more time-consuming read recovery operations. This preliminary action quickly corrects common errors, and only when this proves insufficient does the system proceed to the more time-intensive read recovery stage, optimizing the balance between reliability and processing time.
3Productivity
If error correction operations are enhanced, then data throughput is improved, but device complexity increases
Solution Approach 1:
The read recovery control circuitry serves multiple functions: it manages initial error correction, coordinates read recovery operations, and controls fallback to raw reads. This single multi-functional component improves data throughput through comprehensive error handling without requiring separate dedicated circuits for each error correction stage, thus limiting the increase in device complexity.
Data Source
AI summary
An apparatus includes an error correction component coupled to read recovery control circuitry. The error correction component can be configured to perform one or more initial error correction operations on codewords contained within a managed unit received thereto. The read recovery control circuitry can be configured to receive the error corrected codewords from the error correction component and determine whether codewords among the error corrected codewords contain an uncorrectable error. The read recovery control circuitry can be further configured to determine that a redundant array of independent disks (RAID) codeword included in the plurality of error corrected codewords contains the uncorrectable error, request that codewords among the error corrected codewords that contain the uncorrectable error are rewritten in response to the determination, and cause the plurality of error corrected codewords to be transferred to a host coupleable to the read recovery control circuitry.