Drain-Side Select Gate Threshold Voltage Stabilization
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Solution Overview
Problem
Semi-circle drain side select gate (SC-SGD) memory technology faces inefficiencies due to charge migration and program disturb caused by neighboring electric fields, exacerbated by repeated read operations, leading to shifting of transistor threshold voltage and increased error rates.
Innovation Solution
Incorporating drain-side select gate transistors with a control means to retain a stable transistor threshold voltage, minimizing shifting after read operations by programming the transistors to a specific stable voltage, thereby reducing cumulative read disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If etching technology is used to cut memory holes to form semi-circular shape and separate blocks into strings, then die size is reduced and manufacturing efficiency is improved, but charge migration and program disturb occur due to removal of metal shielding layers
Solution Approach 1:
The patent extracts the problematic metal shielding layer from the semi-circular memory hole structure through selective etching. This removes the harmful component that causes charge migration while preserving the beneficial semi-circular geometry that enables reduced die size and improved manufacturing efficiency.
Solution Approach 2:
The patent introduces a charge trap layer as an intermediary between the remaining metal layers and the channel. This intermediate layer captures and neutralizes stray electric fields that would otherwise cause charge migration, allowing the semi-circular hole design to function reliably without the complete metal shielding.
2Speed
If repeated quick read operations are performed to access memory data, then read speed and access efficiency are improved, but cumulative read disturb exacerbates charge migration and threshold voltage shifting
Solution Approach 1:
The patent applies preliminary action by pre-programming the charge trap layer with compensatory charge before read operations occur. This anticipatory charge neutralization prevents subsequent read operations from causing cumulative threshold voltage shifting, allowing fast reads without reliability degradation.
Solution Approach 2:
The patent converts the harmful effect of read operations (which cause charge migration) into a beneficial effect. By using the read operations to activate the charge trap layer's compensatory mechanism, the system turns the disturbing read cycles into a self-correcting process that stabilizes threshold voltage.
3Ease of manufacture
If metal shielding layers are removed during etching to create semi-circular memory holes, then manufacturing simplicity is improved, but neighboring electric fields directly influence the channel and cause program disturb
Solution Approach 1:
The charge trap layer serves as an intermediary that blocks the harmful neighboring electric fields from directly influencing the channel. This intermediate layer allows the simplified etching process to proceed while neutralizing the harmful electric field effects through charge trapping.
Solution Approach 2:
The patent converts the harmful neighboring electric fields into a beneficial effect by using them to activate the charge trap layer's compensatory mechanism. The electric fields that would normally cause program disturb instead trigger the charge trap layer to neutralize them, turning the harmful factor into a self-correcting feature.
Data Source
AI summary
A memory apparatus and method of operation are provided. The apparatus includes drain-side select gate transistors for coupling to a drain-side of each of a plurality of memory holes of memory cells and configured to retain a transistor threshold voltage. The memory apparatus also includes a control means coupled to the drain-side select gate transistor of each of the plurality of memory holes. The control means is configured to select the transistor threshold voltage of the drain-side select gate transistors as a stable transistor threshold voltage for a grouping of the memory cells to minimize shifting of the transistor threshold voltage following a plurality of read operations of the memory cells. The control means is also configured to program the transistor threshold voltage of the drain-side select gate transistor of the plurality of memory holes associated with the grouping of the memory cells to the stable transistor threshold voltage.