Semiconductor Memory Device Dummy Count Clock Data Output

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The existing semiconductor memory devices face inefficiencies in data output operations, where the actual time taken for data output exceeds the specified time due to the sequential or random selection and output of data from page buffers, leading to longer operation times.

Innovation Solution

The introduction of a dummy count clock generation mechanism, which allows for the pre-output of data to a data line using a dummy count clock before the normal count clock is generated, enabling the generation of a column address and facilitating faster data output by reducing the overall operation time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is output sequentially or randomly from page buffers using normal count clock, then data output operation can be performed, but the actual time taken exceeds the specified time

Engineering Contradiction:

Improvespecification complianceVSAvoiddata output time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent generates a dummy count clock before the normal count clock to pre-output some data to the data line in advance. This preliminary action reduces the actual data output time by having data ready before the specification time window begins, ensuring specification compliance while reducing time loss.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The dummy count clock generates dummy column addresses that are inverted or complemented, creating a preliminary anti-action that prepares the data line in advance. This allows the actual data output to complete within the specification time by having the output mechanism already activated and ready.

Inventive Principle:

Principle #9Preliminary anti-action

2Loss of time

If dummy count clock is generated before normal count clock, then data output time is reduced, but device complexity increases

Engineering Contradiction:

Improvedata output timeVSAvoidcount clock generation complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The count clock generation unit is designed to perform multiple functions: generating both the dummy count clock for pre-output and the normal count clock for actual data output. This multi-functionality reduces device complexity by using a single unified generation unit rather than separate circuits for dummy and normal clock generation.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the dummy count clock generation and normal count clock generation into a single count clock generation unit that operates in different time phases. This combining of functions into one unit simplifies the overall device structure while still achieving the time reduction benefit.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS8767480B2Semiconductor memory device and method of operating the same

Publication Date: 2014.07.01 SK HYNIX INC

AI summary

A semiconductor memory device includes a count clock generation unit for generating a count clock in response to a clock signal and a dummy count clock, a column address generation unit for generating a column address in response to the count clock, and a Y decoder for sending data, stored in a page buffer unit, to a data line in response to the column address.