NAND Flash Memory Light Erase Voltage Control for Data Retention
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Solution Overview
Problem
The progressive deterioration of data holding characteristics in NAND type flash memory cells due to cumulative write and erase operations leads to a decrease in the lower limit of the threshold voltage distribution, causing misreads and data loss, especially as memory cells are miniaturized.
Innovation Solution
A nonvolatile semiconductor memory device that performs a light erase operation by temporarily raising the voltage of the bit line and source line to a light erase voltage before the write verify operation, helping to stabilize the threshold voltage distribution and prevent charge leakage from the gate insulating film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory cell is miniaturized to increase capacity, then the storage density is improved, but the data holding characteristics deteriorate due to progressive threshold voltage distribution degradation
Solution Approach 1:
The patent applies preliminary action by performing a light erase operation before the write verify operation. This preliminary light erase step temporarily raises the bit line and source line voltages to a light erase voltage level, which prevents charge leakage from the gate insulating film during subsequent operations. This advance preventive measure addresses the data holding deterioration issue without requiring changes to the miniaturized cell structure itself.
2Productivity
If the cumulative number of write and erase operations increases, then the programming capability is improved, but the gate insulating film deteriorates progressively causing threshold voltage distribution to fall
Solution Approach 1:
The light erase operation is performed as a preliminary step before write verify operations. By temporarily raising the bit line and source line voltages to the light erase voltage level, the gate insulating film is protected from charge leakage that would otherwise occur during cumulative operations. This preventive action maintains film stability while allowing continued programming capability.
Solution Approach 2:
The patent changes the voltage parameter by introducing a light erase voltage level that is higher than the normal write verify voltage. This parameter change temporarily modifies the electrical conditions during the light erase operation, creating a protective effect on the gate insulating film against charge leakage during subsequent write verify operations.
3Ease of operation
If the lower limit of threshold voltage distribution falls to write verify voltage or less, then the write operation is considered complete, but misreads occur and data holding characteristics deteriorate
Solution Approach 1:
The light erase operation is performed as a preliminary protective measure before the write verify operation. By temporarily raising the voltages on the bit line and source line to the light erase voltage level, charge leakage from the gate insulating film is prevented. This ensures that the threshold voltage distribution remains stable and above the write verify voltage level, preventing misreads while maintaining proper write completion detection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy of write verify operations, reduces misreads, and maintains data integrity by effectively managing the voltage applied to the memory cells, thereby improving the data holding characteristics of NAND type flash memory cells.
Implementation Method 1
a control circuit that controls a voltage applied to the semiconductor layer, the control gate, the bit line, and the source line... temporarily raises, prior to execution of the write verify operation, a voltage of the bit line or the source line to a light erase voltage
Data Source
AI summary
This nonvolatile semiconductor memory device comprises: a word line connected to a control gate; a bit line electrically connected to one end of a NAND cell unit; a source line electrically connected to the other end of the NAND cell unit; and a control circuit that controls a voltage applied to a semiconductor layer, the control gate, the bit line, and the source line.The control circuit is configured to, when performing a write verify operation for determining whether a write operation has been completed or not after finishing the write operation, temporarily raise a voltage of the bit line or the source line to a light erase voltage which is higher than a voltage applied to the bit line or the source line during the write verify operation.