Memory Device Gate Voltage Step and Program Verify Level Adjustment
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Solution Overview
Problem
Memory devices face increased raw bit error rates (RBER) due to threshold voltage shifts caused by temperature variations and program erase cycles, which can exceed the error correction capability of underlying error correction codes (ECC).
Innovation Solution
Adjusting the gate voltage step and program verify level during programming operations based on current temperature and program erase cycles, using a programming adjustment data structure to compensate for threshold voltage distribution shifts, thereby reducing the need for error handling and preventing ECC overload.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate voltage step and program verify level are adjusted based on temperature and program erase cycles, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic adjustment of gate voltage step and program verify level based on real-time temperature sensing and program erase cycle counting. The programming parameters are no longer fixed but adapt continuously to changing operational conditions, resolving the contradiction by making the system responsive to environmental factors that cause threshold voltage shifts.
Solution Approach 2:
The system incorporates feedback mechanisms through temperature sensors and program erase cycle counters that continuously monitor operational conditions. This feedback drives the dynamic adjustment of programming parameters, allowing the system to compensate for threshold voltage shifts and maintain reliability without requiring complex external intervention.
2Device complexity
If default gate voltage step and program verify level are used without adjustment, then device complexity is reduced, but raw bit error rate increases
Solution Approach 1:
The patent changes the programming parameters (gate voltage step and program verify level) based on temperature and program erase cycle conditions. By dynamically modifying these parameters rather than using fixed default values, the system reduces raw bit error rates caused by threshold voltage shifts while maintaining manageable device complexity through systematic parameter adjustment.
Data Source
AI summary
A request to perform a program operation on a memory cell of a memory device is received. A number of program erase cycles (PECs) associated with the memory device is determined. A temperature of the memory device is determined. A gate voltage step adjustment value and a program verify level adjustment value is determined based on the temperature and the number of PECs. A default gate voltage step is adjusted based the gate voltage step adjustment value. A default program verify level is adjusted based the program verify level adjustment value.