SONOS Transistor Switch and Memory Integration via FN Tunneling
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Solution Overview
Problem
Conventional SONOS transistors face challenges in maintaining a stable threshold voltage, leading to misrecognition of memory states and inefficient power consumption when used as both switches and memories, particularly due to the limitations of channel-hot-electron programming and FN tunneling methods.
Innovation Solution
The method employs FN tunneling at the source or drain of a SONOS transistor to change electron states, utilizing gate-induced drain leakage (GIDL) to recognize memory states, allowing for a two-bit memory effect with reduced power consumption and maintaining a stable threshold voltage, enabling the transistor to function as both a switch and a memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If channel-hot-electron programming is used to achieve two-bit memory effect, then memory density is improved, but power consumption increases significantly
Solution Approach 1:
The patent changes the programming mechanism from channel-hot-electron to FN tunneling at source/drain, which fundamentally alters how electrons are injected into the charge storage layer. This parameter change enables two-bit memory effect with lower power consumption by utilizing field-induced tunneling rather than hot carrier generation
Solution Approach 2:
The patent introduces FN tunneling as an intermediary mechanism between the applied voltage and electron storage. By using field-induced tunneling at the source or drain region as the intermediary process, electrons are efficiently injected into the charge storage layer with reduced power consumption compared to direct channel-hot-electron programming
2Quantity of substance
If threshold voltage changes are used to recognize memory state, then memory function is achieved, but transistor switching capability is lost
Solution Approach 1:
The patent segments the memory cell functionality by separating the memory storage function (charge storage layer) from the switching function (transistor channel). The charge storage layer stores electrons to represent memory states, while the transistor maintains its switching capability through controlled channel conduction, allowing both functions to operate independently and simultaneously
Solution Approach 2:
The patent uses the charge storage layer as an intermediary between the control gate and the channel. This intermediary layer modulates the electric field in the channel through its stored charge, enabling memory state recognition through GIDL variation while preserving the transistor's switching capability through independent gate control
3Use of energy by moving object
If FN tunneling is used to program memory, then power consumption is reduced, but two-bit memory effect cannot be achieved
Solution Approach 1:
The patent applies FN tunneling locally at either the source or drain region rather than uniformly across the entire channel. This localized application of tunneling current enables selective electron injection into specific regions of the charge storage layer, achieving the two-bit memory effect while maintaining low power consumption through spatially confined programming operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory density, reduces power consumption, and maintains the threshold voltage, providing a flexible and reliable solution for logic circuits and LCD pixel switches with improved circuit design and reduced misrecognition probabilities.
Implementation Method 1
FN tunneling is carried out on the source or the drain of a SONOS transistor, so as to change the state of electrons stored in an upper charge storage layer
Implementation Method 2
the variation in gate-induced drain leakage (GIDL) is used to recognize the memory state of the drain and source
Data Source
AI summary
There is a method for enabling a SONOS transistor to be used as both a switch and a memory. FN tunneling is carried out through the source or drain of the transistor, so as to further change the state of electrons stored in an upper charge storage layer adjacent to the drain or source, and the variation in gate-induced drain leakage is used to recognize the memory state of the drain and source. A stable threshold voltage of the transistor is always maintained during this operation. The present invention enables one single transistor having dual features of switch and memory, while being provided with a two-bit memory effect, thus providing a higher memory density in comparison with a general transistor.