Assembly Buffer and Bit-Line Driver Circuit for Nonvolatile Memory
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Solution Overview
Problem
Existing memory integrated circuits face issues with data integrity and transfer due to parasitic capacitance, cross-talk, and high threshold voltage problems in low VCC levels, leading to potential data loss and errors during programming and read operations in nonvolatile memory arrays.
Innovation Solution
The implementation of a cross-coupled high-voltage latch with low-voltage n-channel MOS transistors to selectively ground the outputs of high-voltage inverters, ensuring reliable data transfer and preventing data disturbance in assembly buffer circuits, along with a pre-load scheme to maintain data integrity during programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If low VCC levels and finer geometries are used to reduce power consumption and increase integration density, then power efficiency and storage capacity improve, but data integrity deteriorates due to increased parasitic capacitance and cross-talk
Solution Approach 1:
The patent divides the memory circuit into separate high-voltage and low-voltage domains. The assembly buffer operates at high voltage to maintain data integrity, while only the I/O interface operates at low voltage for power efficiency. This segmentation allows each domain to optimize for its specific requirement without compromising the other.
Solution Approach 2:
The patent introduces a voltage translation interface as an intermediary between the high-voltage assembly buffer and low-voltage I/O. This intermediary converts signals between voltage domains, allowing low-voltage operation at the interface while maintaining high-voltage operation internally for data integrity.
2Power
If high-voltage transistors with higher threshold voltage are used in the bit line driver, then programming capability is maintained, but data transfer reliability deteriorates at low VCC levels
Solution Approach 1:
The patent segments the voltage domains so that high-voltage transistors are confined to the assembly buffer where they are needed for programming, while low-voltage transistors handle data transfer operations. This allows high programming capability where needed without compromising data transfer reliability.
Solution Approach 2:
The patent dynamically changes the operating voltage parameter of the assembly buffer to match the I/O voltage domain during data transfer operations. By adjusting the voltage domain to match, reliable data transfer is achieved without requiring high-threshold transistors for the transfer operation itself.
3Area of stationary object
If the assembly buffer and bit line driver are integrated in the same circuit, then area is reduced, but data disturbance increases due to parasitic capacitance and cross-talk
Solution Approach 1:
The patent segments the integrated circuit into distinct high-voltage and low-voltage regions with clear spatial separation. By physically separating the voltage domains and using isolation structures, parasitic capacitance and cross-talk between regions are minimized while maintaining overall integration.
Solution Approach 2:
The patent introduces isolation structures and voltage translation circuits as intermediaries between the assembly buffer and bit line driver. These intermediaries reduce direct coupling and parasitic effects while enabling close integration of the components.
Data Source
AI summary
An assembly buffer and bitline driver circuit has two inverters cross-coupled to form an assembly buffer. A high-voltage latch is formed from cross-coupled high-voltage inverters. A first low-voltage n-channel MOS transistors is coupled to the high-voltage latch to selectively ground the output of the first high-voltage inverter and a second low-voltage n-channel MOS transistors is coupled to the high-voltage latch to selectively ground the output of the other high-voltage inverter. The gate of the first low-voltage n-channel MOS transistor is coupled to one output of one of the inverters forming the assembly buffer latch and the gate of the second low-voltage n-channel MOS transistor is coupled to the output of the other one of the inverters forming the assembly buffer latch. A pre-load circuit is used to prevent data in an unselected circuit from being disturbed.